lab28_new\PipelineCPU\ISE\DataRAM.mif
.........\...........\...\DataRAM.ngc
.........\...........\...\DataRAM.sym
.........\...........\...\DataRAM.v
.........\...........\...\DataRAM.veo
.........\...........\...\DataRAM.vhd
.........\...........\...\DataRAM.vho
.........\...........\...\DataRAM.xco
.........\...........\...\DataRAM_flist.txt
.........\...........\...\DataRAM_readme.txt
.........\...........\...\DataRAM_xmdf.tcl
.........\...........\...\MipsPipelineCPU.bld
.........\...........\...\MipsPipelineCPU.cmd_log
.........\...........\...\MipsPipelineCPU.ise
.........\...........\...\MipsPipelineCPU.ise_ISE_Backup
.........\...........\...\MipsPipelineCPU.lso
.........\...........\...\MipsPipelineCPU.ncd
.........\...........\...\MipsPipelineCPU.ngc
.........\...........\...\MipsPipelineCPU.ngd
.........\...........\...\MipsPipelineCPU.ngr
.........\...........\...\MipsPipelineCPU.ntrc_log
.........\...........\...\MipsPipelineCPU.pad
.........\...........\...\MipsPipelineCPU.par
.........\...........\...\MipsPipelineCPU.pcf
.........\...........\...\MipsPipelineCPU.prj
.........\...........\...\MipsPipelineCPU.restore
.........\...........\...\MipsPipelineCPU.spl
.........\...........\...\MipsPipelineCPU.stx
.........\...........\...\MipsPipelineCPU.sym
.........\...........\...\MipsPipelineCPU.syr
.........\...........\...\mipspipelinecpu.twr
.........\...........\...\mipspipelinecpu.twx
.........\...........\...\MipsPipelineCPU.unroutes
.........\...........\...\MipsPipelineCPU.xpi
.........\...........\...\MipsPipelineCPU.xst
.........\...........\...\MipsPipelineCPU_guide.ncd
.........\...........\...\MipsPipelineCPU_map.map
.........\...........\...\MipsPipelineCPU_map.mrp
.........\...........\...\MipsPipelineCPU_map.ncd
.........\...........\...\MipsPipelineCPU_map.ngm
.........\...........\...\MipsPipelineCPU_pad.csv
.........\...........\...\MipsPipelineCPU_pad.txt
.........\...........\...\MipsPipelineCPU_prev_built.ngd
.........\...........\...\MipsPipelineCPU_summary.html
.........\...........\...\MipsPipelineCPU_summary.xml
.........\...........\...\MipsPipelineCPU_usage.xml
.........\...........\...\xst\dump.xst\MipsPipelineCPU.prj\ntrc.scr
.........\...........\...\...\work\hdllib.ref
.........\...........\...\...\....\vlg07\add__32bits.bin
.........\...........\...\...\....\.....\dffre.bin
.........\...........\...\...\....\...1E\_data_r_a_m.bin
.........\...........\...\...\....\...28\dff.bin
.........\...........\...\...\....\.....\_a_l_u__tb__v.bin
.........\...........\...\...\....\....A\_a_l_u.bin
.........\...........\...\...\....\....F\_mips_pipeline_c_p_u.bin
.........\...........\...\...\....\...30\_decode.bin
.........\...........\...\...\....\....1\_e_x.bin
.........\...........\...\...\....\.....\_i_d.bin
.........\...........\...\...\....\....3\_i_f.bin
.........\...........\...\...\....\....A\dffr.bin
.........\...........\...\...\....\...49\add__4bits__optical.bin
.........\...........\...\...\....\....A\add__4bits.bin
.........\...........\...\...\....\...73\_multi_registers.bin
.........\...........\...\...\....\....C\_instruction_r_o_m.bin
.........\...........\...\_ngo\netlist.lst
.........\...........\...\.xmsgs\map.xmsgs
.........\...........\...\......\ngdbuild.xmsgs
.........\...........\...\......\par.xmsgs
.........\...........\...\......\trce.xmsgs
.........\...........\...\......\xst.xmsgs
.........\...........\SIM\addr.vhd
.........\...........\...\add_32bits.vhd
.........\...........\...\add_32bits.vhd.bak
.........\...........\...\ALU\ALU_tb.v
.........\...........\...\...\ALU_tb2.v
.........\...........\...\alu.cr.mti
.........\...........\...\alu.mpf
.........\...........\...\DataRAM.mif
.........\...........\...\.ecode\Decode_tb.v
.........\...........\...\......\Decode_tb.v.bak
.........\...........\...\IF\IF_tb.v
.........\...........\...\modelsim.ini
.........\...........\...\top\top_tb.v
.........\...........\...\top_tb.v
.........\...........\...\vsim.wlf
.........\...........\...\wlft2x6zxj
.........\...........\...\wlftwjft9m
.........\...........\...\.o