Description: synthesizable verilog rtl implemetation of interpolation filter, for both asic and fpga.
64x interpolation.
interp_filter.v
interp_first.v
interp_second.v
interp_third.v
upsample.v
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File list (Check if you may need any files):
interp_third.v
upsample.v
interp_filter.v
interp_first.v
interp_second.v
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