Description: Xilinx PCIe with DMA, burning into the V5 platform, verified with a pdf document detailed tutorial, windows driver and application interfaces are inside, comprehensive information at a glance
- [pci_core] - pci CORES from foreign web sites get dow
- [PCIE] - pci, pcie related to basic knowledge, in
- [Xilinx_PCIE_DMA] - Xilinx chip on the PCI Express interface
- [Fingerprint] - Using VISUAL BASIC language, a fingerpri
- [mul64] - Verilog implementation of the 64-bit mul
- [hx711] - a code used for move hx711,which based o
File list (Check if you may need any files):
PCI_express_DMA_Freeware_Virtex-5\DMA_Freeware\pcie_ml505esx1_prj\ml505cg\endpoint_blk_plus_v1_5\doc\pcie_blk_plus_ds551.pdf
.................................\............\..................\.......\......................\...\pcie_blk_plus_gsg343.pdf
.................................\............\..................\.......\......................\...\pcie_blk_plus_ug341.pdf
.................................\............\..................\.......\......................\example_design\BMD.v
.................................\............\..................\.......\......................\..............\BMD_64.v
.................................\............\..................\.......\......................\..............\BMD_64_RX_ENGINE.v
.................................\............\..................\.......\......................\..............\BMD_64_TX_ENGINE.v
.................................\............\..................\.......\......................\..............\BMD_EP.v
.................................\............\..................\.......\......................\..............\BMD_EP_MEM.v
.................................\............\..................\.......\......................\..............\BMD_EP_MEM_ACCESS.v
.................................\............\..................\.......\......................\..............\BMD_INTR_CTRL.v
.................................\............\..................\.......\......................\..............\BMD_TO_CTRL.v
.................................\............\..................\.......\......................\..............\EP_MEM.v
.................................\............\..................\.......\......................\..............\pci_exp_1_lane_64b_ep.v
.................................\............\..................\.......\......................\..............\pci_exp_64b_app.v
.................................\............\..................\.......\......................\..............\xilinx_pci_exp_1_lane_ep.v
.................................\............\..................\.......\......................\..............\xilinx_pci_exp_1_lane_ep_product.v
.................................\............\..................\.......\......................\..............\xilinx_pci_exp_blk_plus_1_lane_ep-XC5VLX50T-FF1136-1_ES.ucf
.................................\............\..................\.......\......................\implement\backup_implement.sh
.................................\............\..................\.......\......................\.........\coregen.log
.................................\............\..................\.......\......................\.........\endpoint_blk_plus_v1_5_top.bld
.................................\............\..................\.......\......................\.........\implement.sh
.................................\............\..................\.......\......................\.........\make_ace.sh
.................................\............\..................\.......\......................\.........\novas.rc
.................................\............\..................\.......\......................\.........\pcie_ace.cmd
.................................\............\..................\.......\......................\.........\pcie_x1_plus_v1_5es_imp.ace
.................................\............\..................\.......\......................\.........\results\mapped.map
.................................\............\..................\.......\......................\.........\.......\mapped.mrp
.................................\............\..................\.......\......................\.........\.......\mapped.ncd
.................................\............\..................\.......\......................\.........\.......\mapped.pcf
.................................\............\..................\.......\......................\.........\.......\netlist.lst
.................................\............\..................\.......\......................\.........\.......\ro
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