Description: Assignment 3
Construct VHDL models for 74-139 dual 2-to-4-line decoders using three description styles, i.e., behavioral, dataflow and structural descriptions. (1) Synthesize and (2) simulate these models respectively in the environment of Xilinx ISE and ModelSim simulator. When simulating these models, test vector(s) are required to stimulate the units under test (UUT). Reasonable test vectors are designed and created by your own as sources added to your VHDL project.
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