Description: MIPS CPU with Mulicycle Datapath. This is a custom RISC processor implemented to achieve the function of "lw, sw, add, sub, and, or, beq, j"
Mem.vhd- memory
buffer.vhd- buffer
ALUcon.vhd- Alu controller
pc.vhd- program counter
REG- registers
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File list (Check if you may need any files):
VHDL for Datapath
.................\ALU.vhd
.................\ALUcon.vhd
.................\buffer.vhd
.................\datapath controller.vhd
.................\Mem.vhd
.................\MIPS.vhd
.................\mux.vhd
.................\pc.vhd
.................\REG.vhd
.................\SEandSL.vhd
.................\shift.vhd
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