5_Sets_of_8051_VHDL_Verilog\MIPS_IP\alu.vhd
...........................\.......\alucontrol.vhd
...........................\.......\control.vhd
...........................\.......\datapath.vhd
...........................\.......\dff32.vhd
...........................\.......\leo_mips.vhd
...........................\.......\leo_mips_p.vhd
...........................\.......\mips_clkdiv.vhd
...........................\.......\mips_core.vhd
...........................\.......\mips_ram.vhd
...........................\.......\mips_rom.vhd
...........................\.......\output.coe
...........................\.......\regfile.vhd
...........................\.......\wr_we.vhd
...........................\DW8051_Verilog\DW01_add.v
...........................\..............\DW01_addsub.v
...........................\..............\DW01_cmp2.v
...........................\..............\DW01_sub.v
...........................\..............\DW02_mult.v
...........................\..............\DW8051_alu.v
...........................\..............\DW8051_biu.v
...........................\..............\DW8051_control.v
...........................\..............\DW8051_core.v
...........................\..............\DW8051_cpu.v
...........................\..............\DW8051_intr_0.v
...........................\..............\DW8051_intr_1.v
...........................\..............\DW8051_main_regs.v
...........................\..............\DW8051_op_decoder.v
...........................\..............\DW8051_serial.v
...........................\..............\DW8051_shftreg.v
...........................\..............\DW8051_timer.v
...........................\..............\DW8051_timer2.v
...........................\..............\DW8051_timer_ctr.v
...........................\..............\DW8051_updn_ctr.v
...........................\..............\DW8051_u_ctr_clr.v
...........................\..............\transcript
...........................\..............\DW8051\DW8051_package.inc
...........................\..............\......\DW8051_parameter.v
...........................\..............\......\vssver.scc
...........................\8086IP\alu.vhd
...........................\......\a_table.vhd
...........................\......\biu.vhd
...........................\......\biufsm.vhd
...........................\......\cpu86.vhd
...........................\......\cpu86instr.vhd
...........................\......\cpu86pack.vhd
...........................\......\datapath.vhd
...........................\......\dataregfile.vhd
...........................\......\divider.vhd
...........................\......\d_table.vhd
...........................\......\formatter.vhd
...........................\......\hwmfsm.vhd
...........................\......\hwmon.vhd
...........................\......\ipregister.vhd
...........................\......\multiplier.vhd
...........................\......\m_table.vhd
...........................\......\n_table.vhd
...........................\......\proc.vhd
...........................\......\regshiftmux.vhd
...........................\......\r_table.vhd
...........................\......\segregfile.vhd
...........................\......\top.vhd
...........................\..51_VerilogSource\syn\src\verilog\disp.v
...........................\..................\...\...\.......\oc8051_fpga_top.v
...........................\..................\...\...\.......\oc8051_ram.v
...........................\..................\...\...\.......\oc8051_rom.v
...........................\..................\...\...\.......\read me.txt
...........................\..................\...\out\oc8051.ucf
...........................\..................\...\...\oc8051_top.bit
...........................\..................\...\...\oc8051_top.srm
...........................\..................\...\...\oc8051_top.srs
...........................\..................\...\...\read.me
...........................\..................\...\log\oc8051_top.srr
...........................\..................\.im\rtl_sim\src\veril