Description: DMA controller VHDL code entity dma is
generic
(
ADDR_WIDTH : integer := 16 -- default value
DATA_WIDTH : integer := 16 -- default value
)
port
(
RESET_L : in std_logic
CLK : in std_logic
DRQ_L : in std_logic
DMAACK_L : in std_logic
RDY_L : in std_logic
DACK_L : out std_logic
DMARQ_L : out std_logic
WR_L : inout std_logic
ADDR : inout std_logic_vector(ADDR_WIDTH - 1 downto 0)
DATA : inout std_logic_vector(DATA_WIDTH - 1 downto 0)
)
end dma
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File list (Check if you may need any files):
DMA.vhd
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