Description: Realize the clock odd (11) frequency divider, other odd frequency division as long as recount div1 and div2 parameters will do.
To Search:
File list (Check if you may need any files):
odd_division\odd_div.v
............\odd_div.v.bak
............\odd_division.gise
............\odd_division.ise
............\odd_division.xise
............\odd_div_summary.html
............\test_odd_div.fdo
............\test_odd_div.udo
............\test_odd_div.v
............\test_odd_div_wave.fdo
............\transcript
............\vsim.wlf
............\work\glbl\verilog.asm
............\....\....\_primary.dat
............\....\....\_primary.vhd
............\....\odd_div\verilog.asm
............\....\.......\_primary.dat
............\....\.......\_primary.vhd
............\....\test_odd_div\verilog.asm
............\....\............\_primary.dat
............\....\............\_primary.vhd
............\....\_info
............\odd_division_xdb\tmp
............\work\glbl
............\....\odd_div
............\....\test_odd_div
............\odd_division_xdb
............\work
............\_xmsgs
odd_division
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