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VHDL-FPGA-Verilog
Title:
5-15
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Category:
VHDL-FPGA-Verilog
Tags:
[VHDL]
[源码]
File Size:
8kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
wh
Description:
DDS implementations, in XILINX FPGA verification by. Using ROM.
Downloaders recently:
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(Check if you may need any files):
5-15 ....\dds.v ....\rom_cos.coe ....\rom_cose.xco ....\rom_sin.coe ....\rom_sine.xco
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