Description: FPGA Application Development and Typical examples of code, typical examples 9 SignalTap II functional demo
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典型实例9 SignalTap II 功能演示\典型实例9 SignalTap II 功能演示\S3_WAVE\PROJ\cmp_state.ini
...............................\...............................\.......\....\COUNTER.bsf
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...............................\...............................\.......\....\COUNTER_wave0.jpg
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...............................\...............................\.......\....\div.bsf
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...............................\...............................\.......\....\insystem.bmp
...............................\...............................\.......\....\PROJ.rar
...............................\...............................\.......\....\ROM.bsf
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...............................\...............................\.......\....\serv_req_info.txt
...............................\...............................\.......\....\signal-tap.bmp
...............................\...............................\.......\....\..mulation\modelsim\cyclone_atoms.v
...............................\...............................\.......\....\..........\........\vsim.wlf
...............................\...............................\.......\....\..........\........\wave.do
...............................\...............................\.......\....\..........\........\WAVE.vo
...............................\...............................\.......\....\..........\........\WAVE_modelsim.xrf
...............................\...............................\.......\....\..........\........\wave_test.cr.mti
...............................\...............................\.......\....\..........\........\wave_test.mpf
...............................\...............................\.......\....\..........\........\WAVE_TOP.V
...............................\...............................\.......\....\..........\........\WAVE_v.sdo
...............................\...............................\.......\....\..........\........\work\@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e\verilog.asm
...............................\...............................\.......\....\..........\........\....\................................\_primary.dat
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...............................\...............................\.......\....\..........\........\....\.w@a@v@e\verilog.asm
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...............................\...............................\.......\....\..........\........\....\........\_primary.vhd
...............................\...............................\.......\....\..........\........\....\cyclone_and1\verilog.asm
...............................\...............................\.......\....\..........\........\....\............\_primary.dat
...............................\...............................\.......\....\..........\........\....\............\_primary.vhd
...............................\...............................\.......\....\..........\........\....\............6\verilog.asm
...............................\...............................\.......\....\..........\........\....\.............\_primary.dat
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