Description: Using Verilog language FIR filter, the Xilinx Spartan-6 run through, is a very good program Verlog
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FIR\addr_generater.v
...\delay.v
...\fir.ucf
...\fir.v
...\fir_rom.coe
...\fir_rom_tb.v
...\fir_tb.v
...\fir_top.bit
...\fir_top.v
...\x7seg.v
FIR