Description: pci 32 位 33M slave device interface source code, using verilog language design, the design of their pci soft core of great reference value.
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File list (Check if you may need any files):
pci-32.v
pci-33.v
pci-40.vhd
pci_mini-34.v
pci_mini-34_timing_constraints.sdc
pci_mini_40_timing_constraints.sdc
PCI_Mini_IP_core_Datasheet2.0_oc.pdf
sample_testbench.GIF
sample_timing_constraints.ucf.txt