Description: Eight experiments designed CPU design using the instruction set, write assembly code in order to test all commands and instructions that involve the design of related functions. Design a good test of the assembly code, and then use the Quartus II software supplied DebugController, writing assembler rules. Next, the assembly DebugController software binary code compiled into the memory used, and the 8-bit CPU designed for testing.
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cpu\alu.bsf
...\alu.vhd
...\ar.bsf
...\ar.vhd
...\asynram.bsf
...\asynram.vhd
...\bus_dir.bsf
...\bus_dir.vhd
...\bus_mux.bsf
...\bus_mux.vhd
...\cmp_state.ini
...\controller.bsf
...\controller.vhd
...\cpu.asm.rpt
...\cpu.bdf
...\cpu.done
...\cpu.fit.eqn
...\cpu.fit.rpt
...\cpu.fit.summary
...\cpu.flow.rpt
...\cpu.map.eqn
...\cpu.map.rpt
...\cpu.map.summary
...\cpu.pin
...\cpu.pof
...\cpu.qpf
...\cpu.qsf
...\cpu.qws
...\cpu.sim.rpt
...\cpu.sof
...\cpu.tan.rpt
...\cpu.tan.summary
...\cpu.vhd
...\cpu.vwf
...\db\add_sub_4ih.tdf
...\..\add_sub_5ih.tdf
...\..\add_sub_djh.tdf
...\..\ar.asm.qmsg
...\..\ar.cbx.xml
...\..\ar.cmp.cdb
...\..\ar.cmp.hdb
...\..\ar.cmp.rdb
...\..\ar.cmp.tdb
...\..\ar.cmp0.ddb
...\..\ar.db_info
...\..\ar.eco.cdb
...\..\ar.fit.qmsg
...\..\ar.hier_info
...\..\ar.hif
...\..\ar.map.cdb
...\..\ar.map.hdb
...\..\ar.map.qmsg
...\..\ar.pre_map.cdb
...\..\ar.pre_map.hdb
...\..\ar.psp
...\..\ar.rtlv.hdb
...\..\ar.rtlv_sg.cdb
...\..\ar.rtlv_sg_swap.cdb
...\..\ar.sgdiff.cdb
...\..\ar.sgdiff.hdb
...\..\ar.sld_design_entry.sci
...\..\ar.sld_design_entry_dsc.sci
...\..\ar.syn_hier_info
...\..\ar.tan.qmsg
...\..\ar_cmp.qrpt
...\..\bus_dir.asm.qmsg
...\..\bus_dir.cbx.xml
...\..\bus_dir.cmp.cdb
...\..\bus_dir.cmp.hdb
...\..\bus_dir.cmp.rdb
...\..\bus_dir.cmp.tdb
...\..\bus_dir.cmp0.ddb
...\..\bus_dir.db_info
...\..\bus_dir.eco.cdb
...\..\bus_dir.fit.qmsg
...\..\bus_dir.hier_info
...\..\bus_dir.hif
...\..\bus_dir.map.cdb
...\..\bus_dir.map.hdb
...\..\bus_dir.map.qmsg
...\..\bus_dir.pre_map.cdb
...\..\bus_dir.pre_map.hdb
...\..\bus_dir.psp
...\..\bus_dir.rtlv.hdb
...\..\bus_dir.rtlv_sg.cdb
...\..\bus_dir.rtlv_sg_swap.cdb
...\..\bus_dir.sgdiff.cdb
...\..\bus_dir.sgdiff.hdb
...\..\bus_dir.sld_design_entry.sci
...\..\bus_dir.sld_design_entry_dsc.sci
...\..\bus_dir.syn_hier_info
...\..\bus_dir.tan.qmsg
...\..\bus_dir_cmp.qrpt
...\..\bus_mux.asm.qmsg
...\..\bus_mux.cbx.xml
...\..\bus_mux.cmp.cdb
...\..\bus_mux.cmp.hdb
...\..\bus_mux.cmp.rdb
...\..\bus_mux.cmp.tdb
...\..\bus_mux.cmp0.ddb
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