Description: Design 326 of RAM, the structure shown in Figure 2. Which, adr as address pins, cs, wr, rd, respectively, for the chip select, write and read the pin, din_out to input or output pin. When cs = 0 and wr from low to high (rising) when, din input data is written on the instructions of the unit adr when cs = 0 and rd = 0 时, adr corresponding data element in the data line read dout out. Because when data is written on the rising edge wr, so you can use TEC-CA single pulse button on the platform as a wr.
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asynram\asynram.asm.rpt
.......\asynram.cdf
.......\asynram.done
.......\asynram.fit.eqn
.......\asynram.fit.rpt
.......\asynram.fit.summary
.......\asynram.flow.rpt
.......\asynram.map.eqn
.......\asynram.map.rpt
.......\asynram.map.summary
.......\asynram.pin
.......\asynram.pof
.......\asynram.qpf
.......\asynram.qsf
.......\asynram.qws
.......\asynram.sof
.......\asynram.tan.rpt
.......\asynram.tan.summary
.......\asynram.vhd
.......\cmp_state.ini
.......\db\asynram.asm.qmsg
.......\..\asynram.cbx.xml
.......\..\asynram.cmp.cdb
.......\..\asynram.cmp.hdb
.......\..\asynram.cmp.rdb
.......\..\asynram.cmp.tdb
.......\..\asynram.cmp0.ddb
.......\..\asynram.db_info
.......\..\asynram.eco.cdb
.......\..\asynram.fit.qmsg
.......\..\asynram.hier_info
.......\..\asynram.hif
.......\..\asynram.map.cdb
.......\..\asynram.map.hdb
.......\..\asynram.map.qmsg
.......\..\asynram.pre_map.cdb
.......\..\asynram.pre_map.hdb
.......\..\asynram.psp
.......\..\asynram.rtlv.hdb
.......\..\asynram.rtlv_sg.cdb
.......\..\asynram.rtlv_sg_swap.cdb
.......\..\asynram.sgdiff.cdb
.......\..\asynram.sgdiff.hdb
.......\..\asynram.signalprobe.cdb
.......\..\asynram.sld_design_entry.sci
.......\..\asynram.sld_design_entry_dsc.sci
.......\..\asynram.syn_hier_info
.......\..\asynram.tan.qmsg
.......\..\asynram_cmp.qrpt
.......\db
asynram
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