bsconvert
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.........\..\p2s.db_info
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.........\..\p2s.eds_overflow
.........\..\p2s.fit.qmsg
.........\..\p2s.hier_info
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.........\..\p2s.lpc.rdb
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.........\..\p2s.rtlv.hdb
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.........\..\p2s.sgdiff.cdb
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.........\..\p2s.sim.cvwf
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.........\..\p2s.tmw_info
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.........\..\prev_cmp_p2s.fit.qmsg
.........\..\prev_cmp_p2s.map.qmsg
.........\..\prev_cmp_p2s.qmsg
.........\..\prev_cmp_p2s.sim.qmsg
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.........\..\wed.wsf
.........\incremental_db
.........\..............\compiled_partitions
.........\..............\...................\p2s.root_partition.cmp.atm
.........\..............\...................\p2s.root_partition.cmp.dfp
.........\..............\...................\p2s.root_partition.cmp.hdbx
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.........\..............\...................\p2s.root_partition.cmp.rcf
.........\..............\...................\p2s.root_partition.map.atm
.........\..............\...................\p2s.root_partition.map.dpi
.........\..............\...................\p2s.root_partition.map.hdbx
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.........\..............\README
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.........\p2s.sim.rpt
.........\p2s.sof
.........\p2s.tan.rpt
.........\p2s.tan.summary
.........\p2s.vhd
.........\p2s.vwf
verilog串并转换并串转换.doc
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基于Verilog_HDL的UART串行通讯模块设计及仿真.pdf