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Title: verilog Download
 Description: opencore can bus verilog design file
 Downloaders recently: [More information of uploader zhixiaowen]
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verilog\.svn\all-wcprops
.......\....\entries
.......\....\prop-base\can_defines.v.svn-base
.......\....\.........\can_register.v.svn-base
.......\....\.........\can_registers.v.svn-base
.......\....\.........\can_register_asyn.v.svn-base
.......\....\.........\can_register_asyn_syn.v.svn-base
.......\....\.........\can_register_syn.v.svn-base
.......\....\text-base\can_acf.v.svn-base
.......\....\.........\can_bsp.v.svn-base
.......\....\.........\can_btl.v.svn-base
.......\....\.........\can_crc.v.svn-base
.......\....\.........\can_defines.v.svn-base
.......\....\.........\can_fifo.v.svn-base
.......\....\.........\can_ibo.v.svn-base
.......\....\.........\can_register.v.svn-base
.......\....\.........\can_registers.v.svn-base
.......\....\.........\can_register_asyn.v.svn-base
.......\....\.........\can_register_asyn_syn.v.svn-base
.......\....\.........\can_register_syn.v.svn-base
.......\....\.........\can_top.v.svn-base
.......\....\.........\README.txt.svn-base
.......\can_acf.v
.......\can_bsp.v
.......\can_btl.v
.......\can_crc.v
.......\can_defines.v
.......\can_fifo.v
.......\can_ibo.v
.......\can_register.v
.......\can_registers.v
.......\can_register_asyn.v
.......\can_register_asyn_syn.v
.......\can_register_syn.v
.......\can_top.v
.......\README.txt
.......\.svn\tmp\prop-base
.......\....\...\props
.......\....\...\text-base
.......\....\prop-base
.......\....\props
.......\....\text-base
.......\....\tmp
.......\.svn
verilog
    

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