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Title: Altera-FPGA_CPLD-design Download
 Description: " Altera FPGA-CPLD design" book source code examples. Very suitable for FPGA beginners.
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Altera FPGA-CPLD设计\Example-b3-1\uart_regs\core\myfifo_10.v
....................\............\.........\....\myfifo_10_bb.v
....................\............\.........\....\myfifo_10_wave0.jpg
....................\............\.........\....\myfifo_10_waveforms.html
....................\............\.........\....\myfifo_8.v
....................\............\.........\....\myfifo_8_bb.v
....................\............\.........\....\myfifo_8_wave0.jpg
....................\............\.........\....\myfifo_8_waveforms.html
....................\............\.........\dev\chip_editor.acv
....................\............\.........\...\cmp_state.ini
....................\............\.........\...\db\add_sub_1jh.tdf
....................\............\.........\...\..\add_sub_dhh.tdf
....................\............\.........\...\..\add_sub_ehh.tdf
....................\............\.........\...\..\add_sub_fhh.tdf
....................\............\.........\...\..\add_sub_ihh.tdf
....................\............\.........\...\..\add_sub_rih.tdf
....................\............\.........\...\..\altsyncram_apb1.tdf
....................\............\.........\...\..\altsyncram_mmb1.tdf
....................\............\.........\...\..\a_dpfifo_4nl.tdf
....................\............\.........\...\..\a_dpfifo_rll.tdf
....................\............\.........\...\..\a_fefifo_qve.tdf
....................\............\.........\...\..\dpram_81k.tdf
....................\............\.........\...\..\dpram_h2k.tdf
....................\............\.........\...\..\scfifo_eaq.tdf
....................\............\.........\...\..\scfifo_nbq.tdf
....................\............\.........\...\..\uart_regs-sim.vwf
....................\............\.........\...\..\uart_regs.asm.qmsg
....................\............\.........\...\..\uart_regs.cmp.cdb
....................\............\.........\...\..\uart_regs.cmp.hdb
....................\............\.........\...\..\uart_regs.cmp.rdb
....................\............\.........\...\..\uart_regs.csf.qmsg
....................\............\.........\...\..\uart_regs.db_info
....................\............\.........\...\..\uart_regs.fit.qmsg
....................\............\.........\...\..\uart_regs.fld
....................\............\.........\...\..\uart_regs.fnsim.cdb
....................\............\.........\...\..\uart_regs.fnsim.hdb
....................\............\.........\...\..\uart_regs.hif
....................\............\.........\...\..\uart_regs.icc
....................\............\.........\...\..\uart_regs.map.cdb
....................\............\.........\...\..\uart_regs.map.hdb
....................\............\.........\...\..\uart_regs.map.qmsg
....................\............\.........\...\..\uart_regs.pre_map.hdb
....................\............\.........\...\..\uart_regs.project.hdb
....................\............\.........\...\..\uart_regs.rpp.qmsg
....................\............\.........\...\..\uart_regs.rtlv.hdb
....................\............\.........\...\..\uart_regs.rtlv_rvd.rvd
....................\............\.........\...\..\uart_regs.rtlv_sg.cdb
....................\............\.........\...\..\uart_regs.rtlv_sg_swap.cdb
....................\............\.........\...\..\uart_regs.sgdiff.cdb
....................\............\.........\...\..\uart_regs.sgdiff.hdb
....................\............\.........\...\..\uart_regs.signalprobe.cdb
....................\............\.........\...\..\uart_regs.sim.hdb
....................\............\.........\...\..\uart_regs.sim.qmsg
....................\............\.........\...\..\uart_regs.sim.rdb
....................\............\.........\...\..\uart_regs.tan.qmsg
....................\............\.........\...\..\uart_regs.uart_regs.sld_design_entry.sci
....................\............\.........\...\..\uart_regs_cmp.qrpt
....................\............\.........\...\..\uart_regs_hier_info
....................\............\.........\...\..\uart_regs_sim.qrpt
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