Description: FPGA-based UART communication, and LCD (1602) show the communication status and data communications. DE2-115 development board by ALTERA Company production run, prove that the program is stable and reliable. The clock is 50MHz, language VHDL, state machines.
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File list (Check if you may need any files):
uart_lcd
........\.qsys_edit
........\..........\filters.xml
........\..........\preferences.xml
........\.sopc_builder
........\.............\filters.xml
........\.............\preferences.xml
........\LED_2.bsf
........\PLLJ_PLLSPE_INFO.txt
........\UART_RX.INC
........\UART_RX.SYM
........\UART_RX.TDF
........\UART_TX.INC
........\UART_TX.SYM
........\UART_TX.TDF
........\baud.bsf
........\baud.vhd
........\baud.vhd.bak
........\bpac.vhd
........\chuankou.asm.rpt
........\chuankou.bdf
........\chuankou.bsf
........\chuankou.cdf
........\chuankou.done
........\chuankou.eda.rpt
........\chuankou.fit.rpt
........\chuankou.fit.smsg
........\chuankou.fit.summary
........\chuankou.flow.rpt
........\chuankou.hex
........\chuankou.jdi
........\chuankou.map.rpt
........\chuankou.map.summary
........\chuankou.pin
........\chuankou.qpf
........\chuankou.qsf
........\chuankou.qws
........\chuankou.sof
........\chuankou.sta.rpt
........\chuankou.sta.summary
........\chuankou.vhd
........\chuankou.vhd.bak
........\chuankou_nativelink_simulation.rpt
........\clk_div100.vhd
........\clk_div30.vhd
........\db
........\..\add_sub_7pc.tdf
........\..\add_sub_8pc.tdf
........\..\alt_u_div_a4f.tdf
........\..\altsyncram_23b1.tdf
........\..\altsyncram_7f91.tdf
........\..\chuankou.amm.cdb
........\..\chuankou.analyze_file.qmsg
........\..\chuankou.asm.qmsg
........\..\chuankou.asm.rdb
........\..\chuankou.asm_labs.ddb
........\..\chuankou.cbx.xml
........\..\chuankou.cmp.bpm
........\..\chuankou.cmp.cdb
........\..\chuankou.cmp.hdb
........\..\chuankou.cmp.kpt
........\..\chuankou.cmp.logdb
........\..\chuankou.cmp.rdb
........\..\chuankou.cmp_merge.kpt
........\..\chuankou.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
........\..\chuankou.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
........\..\chuankou.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
........\..\chuankou.db_info
........\..\chuankou.eda.qmsg
........\..\chuankou.fit.qmsg
........\..\chuankou.hier_info
........\..\chuankou.hif
........\..\chuankou.idb.cdb
........\..\chuankou.lpc.html
........\..\chuankou.lpc.rdb
........\..\chuankou.lpc.txt
........\..\chuankou.map.bpm
........\..\chuankou.map.cdb
........\..\chuankou.map.hdb
........\..\chuankou.map.kpt
........\..\chuankou.map.logdb
........\..\chuankou.map.qmsg
........\..\chuankou.map.rdb
........\..\chuankou.map_bb.cdb
........\..\chuankou.map_bb.hdb
........\..\chuankou.map_bb.logdb
........\..\chuankou.pre_map.cdb
........\..\chuankou.pre_map.hdb
........\..\chuankou.root_partition.map.reg_db.cdb
........\..\chuankou.routing.rdb
........\..\chuankou.rpp.qmsg
........\..\chuankou.rtlv.hdb
........\..\chuankou.rtlv_sg.cdb
........\..\chuankou.rtlv_sg_swap.cdb
........\..\chuankou.sgate.rvd
........\..\chuankou.sgate_sm.rvd
........\..\chuankou.sgdiff.cdb
........\..\chuankou.sgdiff.hdb
........\..\chuankou.sld_design_entry.sci
........\..\chuankou.sld_design_entry_dsc.sci
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