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Title: Matrix-keyboard-and-display Download
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  • VHDL-FPGA-Verilog
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  • 1.29mb
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  • 2013-05-22
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 Description: 1, to understand the principles of ordinary 44 keyboard scan. 2, to further deepen the seven segment display understanding of the process. 3, to understand the input/output port definition method.
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Example12\db\exp12.asm.qmsg
.........\..\exp12.cbx.xml
.........\..\exp12.cmp.ecobp
.........\..\exp12.cmp.kpt
.........\..\exp12.cmp.rdb
.........\..\exp12.cmp_merge.kpt
.........\..\exp12.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
.........\..\exp12.cuda_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
.........\..\exp12.db_info
.........\..\exp12.eco.cdb
.........\..\exp12.eda.qmsg
.........\..\exp12.fit.qmsg
.........\..\exp12.hier_info
.........\..\exp12.hif
.........\..\exp12.map.ecobp
.........\..\exp12.map.kpt
.........\..\exp12.map.qmsg
.........\..\exp12.map_bb.hdbx
.........\..\exp12.map_bb.logdb
.........\..\exp12.pre_map.cdb
.........\..\exp12.pre_map.hdb
.........\..\exp12.psp
.........\..\exp12.rtlv.hdb
.........\..\exp12.rtlv_sg.cdb
.........\..\exp12.rtlv_sg_swap.cdb
.........\..\exp12.sgdiff.cdb
.........\..\exp12.sgdiff.hdb
.........\..\exp12.sld_design_entry.sci
.........\..\exp12.sld_design_entry_dsc.sci
.........\..\exp12.sta.qmsg
.........\..\exp12.sta.rdb
.........\..\exp12.syn_hier_info
.........\..\exp12.tiscmp.fastest_slow_1200mv_0c.ddb
.........\..\exp12.tiscmp.fastest_slow_1200mv_85c.ddb
.........\..\exp12.tiscmp.fast_1200mv_0c.ddb
.........\..\exp12.tiscmp.slow_1200mv_0c.ddb
.........\..\exp12.tiscmp.slow_1200mv_85c.ddb
.........\..\exp12.tis_db_list.ddb
.........\..\prev_cmp_exp12.asm.qmsg
.........\..\prev_cmp_exp12.eda.qmsg
.........\..\prev_cmp_exp12.fit.qmsg
.........\..\prev_cmp_exp12.map.qmsg
.........\..\prev_cmp_exp12.qmsg
.........\..\prev_cmp_exp12.sta.qmsg
.........\exp12.asm.rpt
.........\exp12.done
.........\exp12.eda.rpt
.........\exp12.fit.rpt
.........\exp12.fit.smsg
.........\exp12.fit.summary
.........\exp12.flow.rpt
.........\exp12.map.rpt
.........\exp12.map.summary
.........\exp12.pin
.........\exp12.qpf
.........\exp12.qsf
.........\exp12.qws
.........\exp12.sof
.........\exp12.sta.rpt
.........\exp12.sta.summary
.........\exp12.vhd
.........\exp12.vhd.bak
.........\incremental_db\compiled_partitions\exp12.root_partition.cmp.atm
.........\..............\...................\exp12.root_partition.cmp.dfp
.........\..............\...................\exp12.root_partition.cmp.hdbx
.........\..............\...................\exp12.root_partition.cmp.kpt
.........\..............\...................\exp12.root_partition.cmp.logdb
.........\..............\...................\exp12.root_partition.cmp.rcf
.........\..............\...................\exp12.root_partition.map.atm
.........\..............\...................\exp12.root_partition.map.dpi
.........\..............\...................\exp12.root_partition.map.dpi.tmp
.........\..............\...................\exp12.root_partition.map.hdbx
.........\..............\...................\exp12.root_partition.map.kpt
.........\..............\README
.........\simulation\modelsim\exp12.sft
.........\..........\........\exp12.vho
.........\..........\........\exp12_8_1200mv_0c_vhd_slow.sdo
.........\..........\........\exp12_8_1200mv_85c_vhd_slow.sdo
.........\..........\........\exp12_min_1200mv_0c_vhd_fast.sdo
.........\..........\........\exp12_modelsim.xrf
.........\..........\........\exp12_vhd.sdo
.........\timing\primetime\exp12.collections.sdc
.........\......\.........\exp12.constraints.sdc
.........\......\.........\exp12.pt.tcl
.........\......\.........\exp12.vo
.........\......\.........\exp12_8_1200mv_0c_v_slow.sdo
.........\......\.........\exp12_8_1200mv_85c_v_slow.sdo
.........\......\.........\exp12_min_1200mv_0c_v_fast.sdo
.........\......\.........\exp12_v.sdo
.........\incremental_db\compiled_partitions
.........\simulation\modelsim
.........\timing\primetime
.........\db
.........\incremental_db
.........\simulation
.........\timing
Example12
    

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