- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 12kb
- Update:
- 2013-06-06
- Downloads:
- 0 Times
- Uploaded by:
- 罗小夕
Description: FA161 development board to achieve frequency divider function, the procedures for learning FPGA entry procedures, it s not difficult.
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03-分频器
.........\clock.bsf
.........\clock.vhd
.........\db
.........\..\div.cbx.xml
.........\..\div.db_info
.........\..\div.eco.cdb
.........\..\div.sld_design_entry.sci
.........\..\div.sld_design_entry_dsc.sci
.........\..\prev_cmp_div.qmsg
.........\div.done
.........\div.qpf
.........\div.qsf
.........\div.qws
.........\div_sim.bsf
.........\div_sim.vhd
.........\div_top.bdf
.........\div_top.vhd
.........\incremental_db
.........\..............\compiled_partitions
.........\..............\README
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