Description: Verilog prepared with a series of frames, frames and solutions yards speed matching procedures, rather classic!
- [Verilogexamples.Rar] - some very practical Verilog source is th
- [WM8731] - high-quality audio codec WM8731 Verilog
- [turbo[1].Tar] - turbo code verilog procedures Interested
- [dds_ise7.1_su] - using Verilog language signal generator,
- [frameandcrc8] - Reading frame file, analytic frame and C
- [hdb3_proc] - HDB3 coding and decoding, including cloc
- [shift] - E1 to receive some of the major function
- [pcm] - none
- [RX] - PDH a video of the receiving end, VHDL s
- [HDLC_E1] - E1 TO HDLC E1 TO ETHETH
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