Description: Verilog prepared by the simple asynchronous serial completely original, the station can be accessed content
- [ConciseGuide.Rar] - Concise Guide, a very good one large tea
- [uartok] - Serial communication written by verilog
- [VerilogDHLdigitalclock.Rar] - Verilog language used in the preparation
- [OAdocuments.Rar] - OA documentation, good documentation, so
- [xcv] - verilog prepared by the state machine de
- [fifo_datapath] - verilog achieved, and through serial swi
- [verilog.HDL.examples] - many very useful Verilog examples : ADC,
- [UART] - UART serial procedures, verilog statemen
- [RS232] - FPGA realization of RS-232 serial port t
- [FIFO] - Verilog development FIFO, after verifica
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