Description: Verilog Source code for arbitrary waveform generator- simple DDS algorithm codes run on Xilinx Spartan-3E fpga to show output on dac pin.
Please see the included report. its really simple to implement. all source code is given.
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File list (Check if you may need any files):
Codes\FYP v7.6
.....\........\DDS
.....\........\...\_ngo
.....\........\...\....\netlist.lst
.....\........\...\_xmsgs
.....\........\...\......\bitgen.xmsgs
.....\........\...\......\map.xmsgs
.....\........\...\......\ngdbuild.xmsgs
.....\........\...\......\par.xmsgs
.....\........\...\......\pn_parser.xmsgs
.....\........\...\......\trce.xmsgs
.....\........\...\......\xst.xmsgs
.....\........\...\all_variables.wcfg
.....\........\...\arbitrary_rom.mif
.....\........\...\cincodemayo.coe
.....\........\...\coregen_xil_6768_50.cgc
.....\........\...\coregen_xil_6768_50.cgp
.....\........\...\DAC_Control.v
.....\........\...\dcm.cmd_log
.....\........\...\dcm.spl
.....\........\...\dcm.sym
.....\........\...\dcm.tfi
.....\........\...\dcm.v
.....\........\...\dcm_200MHz.v
.....\........\...\dcm_arwz.ucf
.....\........\...\DDS.gise
.....\........\...\DDS.xise
.....\........\...\dds_fm_am.bit
.....\........\...\dds_rom.cfi
.....\........\...\dds_rom.mcs
.....\........\...\dds_rom.prm
.....\........\...\dds_rom.sig
.....\........\...\dds_tb.v
.....\........\...\dds_tb_beh.prj
.....\........\...\dds_tb_isim_beh.exe
.....\........\...\dds_tb_isim_beh.wdb
.....\........\...\dds_top 2.bit
.....\........\...\dds_top FINAL.bit
.....\........\...\dds_top.bgn
.....\........\...\dds_top.bit
.....\........\...\dds_top.bld
.....\........\...\dds_top.cmd_log
.....\........\...\dds_top.drc
.....\........\...\dds_top.lso
.....\........\...\dds_top.ncd
.....\........\...\dds_top.ngc
.....\........\...\dds_top.ngd
.....\........\...\dds_top.ngr
.....\........\...\dds_top.pad
.....\........\...\dds_top.par
.....\........\...\dds_top.pcf
.....\........\...\dds_top.prj
.....\........\...\dds_top.ptwx
.....\........\...\dds_top.stx
.....\........\...\dds_top.syr
.....\........\...\dds_top.twr
.....\........\...\dds_top.twx
.....\........\...\dds_top.ucf
.....\........\...\dds_top.unroutes
.....\........\...\dds_top.ut
.....\........\...\dds_top.v
.....\........\...\dds_top.xpi
.....\........\...\dds_top.xst
.....\........\...\dds_top_beh.prj
.....\........\...\dds_top_bitgen.xwbt
.....\........\...\dds_top_envsettings.html
.....\........\...\dds_top_guide.ncd
.....\........\...\dds_top_isim_beh.exe
.....\........\...\dds_top_map.map
.....\........\...\dds_top_map.mrp
.....\........\...\dds_top_map.ncd
.....\........\...\dds_top_map.ngm
.....\........\...\dds_top_map.xrpt
.....\........\...\dds_top_ngdbuild.xrpt
.....\........\...\dds_top_pad.csv
.....\........\...\dds_top_pad.txt
.....\........\...\dds_top_par.xrpt
.....\........\...\dds_top_summary.html
.....\........\...\dds_top_summary.xml
.....\........\...\dds_top_usage.xml
.....\........\...\dds_top_xst.xrpt
.....\........\...\dds_v4.cfi
.....\........\...\dds_v4.mcs
.....\........\...\dds_v4.prm
.....\........\...\dds_v4.sig
.....\........\...\exp_rom.mif
.....\........\...\fuse.log
.....\........\...\ipcore_dir
.....\........\...\..........\.lso
.....\........\...\..........\_xmsgs
.....\........\...\..........\......\netgen.xmsgs
.....\........\...\..........\......\ngcbuild.xmsgs
.....\........\...\..........\......\pn_parser.xmsgs
.....\........\...\..........\......\xst.xmsgs
.....\........\...\..........\arb2.asy
.....\........\...\..........\arb2.gise
.....\........\...\..........\arb2.ncf
.....\........\...\..........\arb2.ngc
.....\........\...\..........\arb2.sym
.....\........\...\..........\arb2.v
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