Description: CPU design is realized by VHDL Language, the project contains the test waveform. Contains the CPU design documents, such as directives format, instructions for each function module and test sequence. The project can run directly downloaded to the experiment.
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File list (Check if you may need any files):
CPU设计文档.pdf
cpu设计与实践\.lso
.............\calculate.vhd
.............\calculate_summary.html
.............\clock.vhd
.............\clock_summary.html
.............\cpu.bgn
.............\cpu.bit
.............\cpu.bld
.............\cpu.cel
.............\cpu.cmd_log
.............\cpu.drc
.............\cpu.fdo
.............\cpu.ise
.............\cpu.ise_ISE_Backup
.............\cpu.lfp
.............\cpu.lso
.............\cpu.ncd
.............\cpu.ngc
.............\cpu.ngd
.............\cpu.ngr
.............\cpu.ntrc_log
.............\cpu.pad
.............\cpu.par
.............\cpu.pcf
.............\cpu.prj
.............\cpu.stx
.............\cpu.syr
.............\cpu.twr
.............\cpu.twx
.............\cpu.ucf
.............\cpu.udo
.............\cpu.unroutes
.............\cpu.ut
.............\cpu.vhd
.............\cpu.xpi
.............\cpu.xst
.............\cpu_guide.ncd
.............\cpu_map.map
.............\cpu_map.mrp
.............\cpu_map.ncd
.............\cpu_map.ngm
.............\cpu_pad.csv
.............\cpu_pad.txt
.............\cpu_prev_built.ngd
.............\cpu_summary.html
.............\cpu_summary.xml
.............\cpu_usage.xml
.............\cpu_vhdl.prj
.............\device_usage_statistics.html
.............\getir.vhd
.............\Mcontrol.v
.............\Mcontrol.vhd
.............\Mcontrol_summary.html
.............\Mmanage.vhd
.............\netgen\synthesis\cpu_synthesis.nlf
.............\......\.........\cpu_synthesis.vhd
.............\pepExtractor.prj
.............\results.txt
.............\rewrite.udo
.............\rewrite.vhd
.............\testcal.ant
.............\testcal.fdo
.............\testcal.jhd
.............\testcal.tbw
.............\testcal.udo
.............\testcal.xwv
.............\testcal.xwv_bak
.............\testcal_bencher.prj
.............\testclock.ant
.............\testclock.fdo
.............\testclock.jhd
.............\testclock.tbw
.............\testclock.udo
.............\testclock.xwv
.............\testclock.xwv_bak
.............\testcpu.ant
.............\testcpu.fdo
.............\testcpu.jhd
.............\testcpu.tbw
.............\testcpu.udo
.............\testcpu.vhw
.............\testcpu.xwv
.............\testcpu.xwv_bak
.............\testcpu_bencher.prj
.............\testgetir.ant
.............\testgetir.fdo
.............\testgetir.jhd
.............\testgetir.tbw
.............\testgetir.udo
.............\testgetir.xwv
.............\testgetir.xwv_bak
.............\testgetir2_bencher.prj
.............\testMcontrol.ant
.............\testMcontrol.fdo
.............\testMcontrol.jhd
.............\testMcontrol.tbw
.............\testMcontrol.udo
.............\testMcontrol.xwv
.............\testMcontrol.xwv_bak