Description: FPGA implementation using Altera modulation and demodulation of 2ASK, containing detailed notes and complete project
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File list (Check if you may need any files):
2ASK
....\pro
....\sim
....\...\two_ASK.cr.mti
....\...\two_ASK.mpf
....\...\vsim.wlf
....\...\work
....\...\....\@a@s@k_two
....\...\....\..........\_primary.dat
....\...\....\..........\_primary.dbs
....\...\....\..........\_primary.vhd
....\...\....\..........\verilog.asm
....\...\....\..........\verilog.rw
....\...\....\_info
....\...\....\_temp
....\...\....\.....\vlog0kq5x6
....\...\....\.....\vlog903jr7
....\...\....\.....\vlogatj86b
....\...\....\.....\vlogb55i87
....\...\....\.....\vlogg7bv0e
....\...\....\.....\vlogggbvxd
....\...\....\.....\vlogiinv63
....\...\....\.....\vlogivnv33
....\...\....\.....\vlogrxdesq
....\...\....\.....\vlogy0b0dd
....\...\....\.....\vlogy2qk13
....\...\....\.....\vlogybqky2
....\...\....\_vmake
....\...\....\tb_two_@a@s@k
....\...\....\.............\_primary.dat
....\...\....\.............\_primary.dbs
....\...\....\.............\_primary.vhd
....\...\....\.............\verilog.asm
....\...\....\.............\verilog.rw
....\...\....\two_@a@s@k
....\...\....\..........\_primary.dat
....\...\....\..........\_primary.dbs
....\...\....\..........\_primary.vhd
....\...\....\..........\verilog.asm
....\...\....\..........\verilog.rw
....\...\....\two_@a@s@k_two
....\...\....\..............\_primary.dat
....\...\....\..............\_primary.dbs
....\...\....\..............\_primary.vhd
....\...\....\..............\verilog.asm
....\...\....\..............\verilog.rw
....\src
....\...\ASK_two.v
....\...\ASK_two.v.bak
....\...\src
....\...\...\tb_ASK.v.bak
....\...\tb_ASK.v
....\...\tb_two_ASK.v
....\...\tb_two_ASK.v.bak
....\...\two_ASK.v
....\...\two_ASK.v.bak
....\...\two_ASK_two.v
....\...\two_ASK_two.v.bak
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