Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: cic_cq Download
 Description: In the Altera platform using Verilog hardware description language CIC decimation filter, contains the complete project code, has been adopted by simulation, can be used directly in practice
 Downloaders recently: [More information of uploader 汪少锋]
 To Search:
File list (Check if you may need any files):
 

cic_cq
......\derivative_filter
......\.................\data_generate.v
......\.................\der_filter_27sub.v
......\.................\derivative_filter.v
......\.................\derivative_filter_tb.v
......\pro
......\scr
......\...\cic
......\...\...\pro
......\...\...\scr
......\...\...\...\CIC抽取滤波器.doc
......\...\...\...\CIC抽取滤波器.docx
......\...\...\...\cic.cr.mti
......\...\...\...\cic.mpf
......\...\...\...\cic_dec24.v
......\...\...\...\cic_dec_arithmetic.v
......\...\...\...\der_filter_27sub.v
......\...\...\...\derivative_filter.v
......\...\...\...\derivative_filter.v.bak
......\...\...\...\fir_analyz_out_data.m
......\...\...\...\fir_analyz_signal_data.m
......\...\...\...\monopole_integrator_first.v
......\...\...\...\multilevel_der_filter.v
......\...\...\...\multilevel_integrator.v
......\...\...\...\out_data.dat
......\...\...\...\quantization.m
......\...\...\...\signal_1m.dat
......\...\...\...\signal_1m.dat.bak
......\...\...\...\signal_data.dat
......\...\...\...\signal_gen0.v
......\...\...\...\signal_gen0.v.bak
......\...\...\...\sin_1MHz_gen.m
......\...\...\...\tb_cic.v
......\...\...\...\vsim.wlf
......\...\...\...\work
......\...\...\...\....\_info
......\...\...\...\....\_temp
......\...\...\...\....\_vmake
......\...\...\...\....\cic_dec24
......\...\...\...\....\.........\_primary.dat
......\...\...\...\....\.........\_primary.dbs
......\...\...\...\....\.........\_primary.vhd
......\...\...\...\....\.........\verilog.asm
......\...\...\...\....\.........\verilog.rw
......\...\...\...\....\cic_dec_arithmetic
......\...\...\...\....\..................\_primary.dat
......\...\...\...\....\..................\_primary.dbs
......\...\...\...\....\..................\_primary.vhd
......\...\...\...\....\..................\verilog.asm
......\...\...\...\....\..................\verilog.rw
......\...\...\...\....\der_filter_27sub
......\...\...\...\....\................\_primary.dat
......\...\...\...\....\................\_primary.dbs
......\...\...\...\....\................\_primary.vhd
......\...\...\...\....\................\verilog.asm
......\...\...\...\....\................\verilog.rw
......\...\...\...\....\derivative_filter
......\...\...\...\....\.................\_primary.dat
......\...\...\...\....\.................\_primary.dbs
......\...\...\...\....\.................\_primary.vhd
......\...\...\...\....\.................\verilog.asm
......\...\...\...\....\.................\verilog.rw
......\...\...\...\....\monopole_integrator_first
......\...\...\...\....\.........................\_primary.dat
......\...\...\...\....\.........................\_primary.dbs
......\...\...\...\....\.........................\_primary.vhd
......\...\...\...\....\.........................\verilog.asm
......\...\...\...\....\.........................\verilog.rw
......\...\...\...\....\multilevel_der_filter
......\...\...\...\....\.....................\_primary.dat
......\...\...\...\....\.....................\_primary.dbs
......\...\...\...\....\.....................\_primary.vhd
......\...\...\...\....\.....................\verilog.asm
......\...\...\...\....\.....................\verilog.rw
......\...\...\...\....\multilevel_integrator
......\...\...\...\....\.....................\_primary.dat
......\...\...\...\....\.....................\_primary.dbs
......\...\...\...\....\.....................\_primary.vhd
......\...\...\...\....\.....................\verilog.asm
......\...\...\...\....\.....................\verilog.rw
......\...\...\...\....\signal_gen0
......\...\...\...\....\...........\_primary.dat
......\...\...\...\....\...........\_primary.dbs
......\...\...\...\....\...........\_primary.vhd
......\...\...\...\....\...........\verilog.asm
......\...\...\...\....\...........\verilog.rw
......\...\...\...\....\tb_cic
......\...\...\...\....\......\_primary.dat
......\...\...\...\....\......\_primary.dbs
......\...\...\...\....\......\_primary.vhd
......\...\...\...\....\......\verilog.asm
......\...\...\...\....\......\verilog.rw
......\...\...\...\~$$新建 Microsoft Visio Drawi

CodeBus www.codebus.net