Description: In the Altera platform using Verilog hardware description language CIC interpolation filter, through the simulation in Modelsim software, including the complete project code, can be directly downloaded to the FPGA operation
To Search:
File list (Check if you may need any files):
cic_cz
......\pro
......\scr
......\...\CIC插值滤波器.doc
......\...\CIC插值滤波器.docx
......\...\cic.cr.mti
......\...\cic.mpf
......\...\cic_interp24.v
......\...\cic_interp_arithmetic.v
......\...\derivative_filter.v
......\...\fir_analyz_out_data.m
......\...\fir_analyz_signal_data.m
......\...\monopole_integrator_first.v
......\...\multilevel_der_filter.v
......\...\multilevel_integrator.v
......\...\out_data.dat
......\...\signal_1m.dat
......\...\signal_data.dat
......\...\signal_gen0.v
......\...\sin_gen.m
......\...\tb_cic.v
......\...\vsim.wlf
......\...\work
......\...\....\_info
......\...\....\_temp
......\...\....\.....\vlogkdkhyi
......\...\....\.....\vlogrqi595
......\...\....\_vmake
......\...\....\cic_interp24
......\...\....\............\_primary.dat
......\...\....\............\_primary.dbs
......\...\....\............\_primary.vhd
......\...\....\............\verilog.asm
......\...\....\............\verilog.rw
......\...\....\cic_interp_arithmetic
......\...\....\.....................\_primary.dat
......\...\....\.....................\_primary.dbs
......\...\....\.....................\_primary.vhd
......\...\....\.....................\verilog.asm
......\...\....\.....................\verilog.rw
......\...\....\derivative_filter
......\...\....\.................\_primary.dat
......\...\....\.................\_primary.dbs
......\...\....\.................\_primary.vhd
......\...\....\.................\verilog.asm
......\...\....\.................\verilog.rw
......\...\....\monopole_integrator_first
......\...\....\.........................\_primary.dat
......\...\....\.........................\_primary.dbs
......\...\....\.........................\_primary.vhd
......\...\....\.........................\verilog.asm
......\...\....\.........................\verilog.rw
......\...\....\multilevel_der_filter
......\...\....\.....................\_primary.dat
......\...\....\.....................\_primary.dbs
......\...\....\.....................\_primary.vhd
......\...\....\.....................\verilog.asm
......\...\....\.....................\verilog.rw
......\...\....\multilevel_integrator
......\...\....\.....................\_primary.dat
......\...\....\.....................\_primary.dbs
......\...\....\.....................\_primary.vhd
......\...\....\.....................\verilog.asm
......\...\....\.....................\verilog.rw
......\...\....\signal_gen0
......\...\....\...........\_primary.dat
......\...\....\...........\_primary.dbs
......\...\....\...........\_primary.vhd
......\...\....\...........\verilog.asm
......\...\....\...........\verilog.rw
......\...\....\tb_cic
......\...\....\......\_primary.dat
......\...\....\......\_primary.dbs
......\...\....\......\_primary.vhd
......\...\....\......\verilog.asm
......\...\....\......\verilog.rw
......\...\无标题.png
......\...\滤波器操作说明(抽取和插值).doc
......\...\滤波器操作说明.doc
......\...\第八章__信号的抽取与插值.pdf
......\sim
Download