Description: NC divider, with the words written in VERILOG HDL, can achieve any integer multiple of the input clock frequency, contains the entire project file.
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实验十 数控分频器的设计\cmp_state.ini
.......................\db\dvf.asm.qmsg
.......................\..\dvf.asm_labs.ddb
.......................\..\dvf.cbx.xml
.......................\..\dvf.cmp.cdb
.......................\..\dvf.cmp.hdb
.......................\..\dvf.cmp.kpt
.......................\..\dvf.cmp.logdb
.......................\..\dvf.cmp.rdb
.......................\..\dvf.cmp.tdb
.......................\..\dvf.cmp0.ddb
.......................\..\dvf.cmp2.ddb
.......................\..\dvf.db_info
.......................\..\dvf.eco.cdb
.......................\..\dvf.fit.qmsg
.......................\..\dvf.hier_info
.......................\..\dvf.hif
.......................\..\dvf.lpc.html
.......................\..\dvf.lpc.rdb
.......................\..\dvf.lpc.txt
.......................\..\dvf.map.cdb
.......................\..\dvf.map.hdb
.......................\..\dvf.map.logdb
.......................\..\dvf.map.qmsg
.......................\..\dvf.pre_map.cdb
.......................\..\dvf.pre_map.hdb
.......................\..\dvf.rtlv.hdb
.......................\..\dvf.rtlv_sg.cdb
.......................\..\dvf.rtlv_sg_swap.cdb
.......................\..\dvf.sgdiff.cdb
.......................\..\dvf.sgdiff.hdb
.......................\..\dvf.sld_design_entry.sci
.......................\..\dvf.sld_design_entry_dsc.sci
.......................\..\dvf.syn_hier_info
.......................\..\dvf.tan.qmsg
.......................\..\dvf.tis_db_list.ddb
.......................\..\dvf_global_asgn_op.abo
.......................\..\prev_cmp_dvf.asm.qmsg
.......................\..\prev_cmp_dvf.fit.qmsg
.......................\..\prev_cmp_dvf.map.qmsg
.......................\..\prev_cmp_dvf.qmsg
.......................\..\prev_cmp_dvf.tan.qmsg
.......................\dvf.asm.rpt
.......................\dvf.bdf
.......................\dvf.cdf
.......................\dvf.done
.......................\dvf.dpf
.......................\dvf.fit.eqn
.......................\dvf.fit.rpt
.......................\dvf.fit.smsg
.......................\dvf.fit.summary
.......................\dvf.flow.rpt
.......................\dvf.map.eqn
.......................\dvf.map.rpt
.......................\dvf.map.summary
.......................\dvf.pin
.......................\dvf.pof
.......................\dvf.qpf
.......................\dvf.qsf
.......................\dvf.qws
.......................\dvf.sim.rpt
.......................\dvf.sof
.......................\dvf.tan.rpt
.......................\dvf.tan.summary
.......................\dvf.vwf
.......................\dvf_assignment_defaults.qdf
.......................\incremental_db\compiled_partitions\dvf.root_partition.map.kpt
.......................\..............\README
.......................\int_div.bsf
.......................\int_div.v
.......................\key_led.bsf
.......................\key_led.v
.......................\pulse.bsf
.......................\pulse.v
.......................\_desktop.ini
.......................\incremental_db\compiled_partitions
.......................\db
.......................\incremental_db
实验十 数控分频器的设计
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