- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 4kb
- Update:
- 2014-07-18
- Downloads:
- 0 Times
- Uploaded by:
- 刘诗男
Description: Based on an arbitrary dividing vhdl procedures, adjustable duty cycle,
To Search:
File list (Check if you may need any files):
cnt1_fenpin
...........\cnt1.qpf
...........\cnt1.qsf
...........\cnt1.qws
...........\cnt1.vhd
...........\db
...........\..\cnt1.db_info
...........\..\cnt1.eco.cdb
...........\..\cnt1.sld_design_entry.sci
Download