使用verilog以及VHDL编写的将串口数据转换为32位并口数据\serial ports2\ my_first_fpga\db\my_first_fpga_top.eco.cdb
.....................................................\.............\..............\..\my_first_fpga_top.sld_design_entry.sci
.....................................................\.............\..............\my_first_fpga.qpf
.....................................................\.............\..............\my_first_fpga.qws
.....................................................\.............\db\add_sub_gub.tdf
.....................................................\.............\..\altsyncram_9pf1.tdf
.....................................................\.............\..\alt_synch_pipe_oc8.tdf
.....................................................\.............\..\alt_synch_pipe_pc8.tdf
.....................................................\.............\..\a_fefifo_ctc.tdf
.....................................................\.............\..\a_fefifo_htc.tdf
.....................................................\.............\..\a_gray2bin_q4b.tdf
.....................................................\.............\..\a_graycounter_u06.tdf
.....................................................\.............\..\cntr_cta.tdf
.....................................................\.............\..\dcfifo_mmc1.tdf
.....................................................\.............\..\dffpipe_gd9.tdf
.....................................................\.............\..\dffpipe_id9.tdf
.....................................................\.............\..\dffpipe_jd9.tdf
.....................................................\.............\..\dpram_jvr.tdf
.....................................................\.............\..\serialports.asm.qmsg
.....................................................\.............\..\serialports.cbx.xml
.....................................................\.............\..\serialports.cmp.bpm
.....................................................\.............\..\serialports.cmp.cdb
.....................................................\.............\..\serialports.cmp.ecobp
.....................................................\.............\..\serialports.cmp.hdb
.....................................................\.............\..\serialports.cmp.logdb
.....................................................\.............\..\serialports.cmp.rdb
.....................................................\.............\..\serialports.cmp.tdb
.....................................................\.............\..\serialports.cmp0.ddb
.....................................................\.............\..\serialports.cmp_bb.cdb
.....................................................\.............\..\serialports.cmp_bb.hdb
.....................................................\.............\..\serialports.cmp_bb.logdb
.....................................................\.............\..\serialports.cmp_bb.rcf
.....................................................\.............\..\serialports.dbp
.....................................................\.............\..\serialports.db_info
.....................................................\.............\..\serialports.eco.cdb
.....................................................\.............\..\serialports.fit.qmsg
.....................................................\.............\..\serialports.hier_info
.....................................................\.............\..\serialports.hif
.....................................................\.............\..\serialports.map.bpm
.....................................................\.............\..\serialports.map.cdb
.....................................................\.............\..\serialports.map.ecobp
.....................................................\.............\..\serialports.map.hdb
.....................................................\.............\..\serialports.map.logdb
.....................................................\.............\..\serialports.map.qmsg
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