- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 16kb
- Update:
- 2014-04-07
- Downloads:
- 0 Times
- Uploaded by:
- 潘健森
Description: A simple stopwatch based on VHDL, including key debounce module, digital decoder, timers and other modules. Directly applicable to basys2 and nexys3 two development boards. After changing the ucf file applicable to other development board
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File list (Check if you may need any files):
timer
.....\BASYS2
.....\......\btn_xd.vhd
.....\......\data_control.vhd
.....\......\seg_drive.vhd
.....\......\timer.vhd
.....\......\top.bit
.....\......\top.ucf
.....\......\top.vhd
.....\NEXYS3
.....\......\btn_xd.vhd
.....\......\data_control.vhd
.....\......\seg_drive.vhd
.....\......\timer.vhd
.....\......\top.bit
.....\......\top.ucf
.....\......\top.vhd
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