Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: time60 Download
 Description: A small footprint clock generator Verilog code, is worth learning
 Downloaders recently: [More information of uploader wangzao]
 To Search:
File list (Check if you may need any files): 
 

time60.v

CodeBus www.codebus.net