Description: Implements a 16550/16750 UART. The UART core is fully based on another OpenCores project: UART_16750 by Sebastian Witt.
Please find there the documentation regarding the Uart core.
The interface is now compatible with a 8-bit WishBone bus.
With GHDL simulator simply run:
./ghdl_uart.bat
Using any other simulator, before starting the simulation the following perl script must be run:
uart_test_stim.pl > filename.txt
where filename.txt is the name selected in generic stim_file inside wb8_uart_transactor.vhd.
A correct simulation should exit with an assertion message simulation END .
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File list (Check if you may need any files):
61549803wb_uart_latest.tar
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