CoreUartTest\component\Actel\DirectCore\COREUART\5.5.101\COREUART.cxf
............\.........\work\DESIGN_FIRMWARE\DESIGN_FIRMWARE.cxf
............\.........\....\...............\DESIGN_FIRMWARE.sdb
............\.........\....\.......IO\DESIGN_IO.cxf
............\.........\....\.........\DESIGN_IO.sdb
............\.........\....\uart1\uart1.cxf
............\.........\....\.....\uart1.sdb
............\.........\....\.....\uart1.v
............\.........\....\.....\....._0\coreparameters.v
............\.........\....\.....\.......\mti\scripts\wave_vlog.do
............\.........\....\.....\.......\rtl\vlog\core\Clock_gen.v
............\.........\....\.....\.......\...\....\....\CoreUART.v
............\.........\....\.....\.......\...\....\....\fifo_256x8_pa3e.v
............\.........\....\.....\.......\...\....\....\Rx_async.v
............\.........\....\.....\.......\...\....\....\Tx_async.v
............\.........\....\.....\.......\...\....\test\user\testbnch.v
............\.........\....\.....\.......\uart1_uart1_0_COREUART.cxf
............\.........\....\.....\uart1_manifest.txt
............\.........\....\...._SmartDesign\COREUART_0\coreparameters.v
............\.........\....\................\..........\mti\scripts\wave_vlog.do
............\.........\....\................\..........\rtl\vlog\core\Clock_gen.v
............\.........\....\................\..........\...\....\....\CoreUART.v
............\.........\....\................\..........\...\....\....\fifo_256x8_pa3e.v
............\.........\....\................\..........\...\....\....\Rx_async.v
............\.........\....\................\..........\...\....\....\Tx_async.v
............\.........\....\................\..........\...\....\test\user\testbnch.v
............\.........\....\................\..........\uart_SmartDesign_COREUART_0_COREUART.cxf
............\.........\....\................\datasheet.xsl
............\.........\....\................\drcss.xsl
............\.........\....\................\uart_SmartDesign.cxf
............\.........\....\................\uart_SmartDesign.sdb
............\.........\....\................\uart_SmartDesign.v
............\.........\....\................\uart_SmartDesign_DataSheet.xml
............\.........\....\................\uart_SmartDesign_DRC.xml
............\.........\....\................\uart_SmartDesign_manifest.txt
............\CoreUartTest.prjx
............\designer\impl1\run_designer_tool.log
............\........\.....\run_designer_tool.tcl
............\........\.....\run_pinrpt.tcl
............\........\.....\uart_SmartDesign.adb
............\........\.....\.................dtf\verify.log
............\........\.....\uart_SmartDesign.ide_des
............\........\.....\uart_SmartDesign.pdb
............\........\.....\uart_SmartDesign.pdb.depends
............\........\.....\uart_SmartDesign.tcl
............\........\.....\uart_SmartDesign_compile_log.rpt
............\........\.....\uart_SmartDesign_compile_report.txt
............\........\.....\.................fp\$$FlashPro_97574.L$$
............\........\.....\...................\projectData\uart_SmartDesign.pdb
............\........\.....\...................\uart_SmartDesign.pro
............\........\.....\uart_SmartDesign_fp.tcl
............\........\.....\uart_SmartDesign_globalnet_report.txt
............\........\.....\uart_SmartDesign_globalusage_report.txt
............\........\.....\uart_SmartDesign_iobank_report.txt
............\........\.....\uart_SmartDesign_maxdelay_timingviolations_report.txt
............\........\.....\uart_SmartDesign_maxdelay_timing_report.txt
............\........\.....\uart_SmartDesign_mindelay_timingviolations_report.txt
............\........\.....\uart_SmartDesign_mindelay_timing_report.txt
............\........\.....\uart_SmartDesign_placeroute_log.rpt
............\........\.....\uart_SmartDesign_place_and_route_report.txt
............\........\.....\uart_SmartDesign_prgdata_log.rpt
............\........\.....\uart_SmartDesign_report_pin_byname.txt
............\........\.....\uart_SmartDesign_report_pin_bynu