Description: Use Verilog HDL language design and implementation of digital systems design stopwatch, covering schematic design, text, design, and simulation waveform, and there is a corresponding report. The report also includes a BCD/7 segment decoder IC 74LS47 simulation, single-tube type stable operating point voltage divider bias circuit simulation and 8 quiz Responder circuit design
To Search:
File list (Check if you may need any files):
second\报告.doc
second
......\LIB.DLS
......\U2600752.DLS
......\watch.acf
......\watch.fit
......\watch.hif
......\watch.jam
......\watch.jbc
......\watch.mmf
......\watch.ndb
......\watch.pin
......\watch.pof
......\watch.rpt
......\watch.scf
......\watch.snf
......\watch.v
Download