Description: The experimental requirements:
(1) to draw the 5 cascaded carry and circuit diagrams of carry look ahead adder, required to indicate signal input, output signal, the intermediate signal and all other related in the figure, and the signal should be named annotation and figure one one corresponding
(2) can not be used textbooks in the FOR loop statement, the assignment statement of VHDL should be and the circuit in figure one one correspond
(3) VHDL code and the simulation waveform to save.
(4) on the carry lookahead adder, can reference books P160 design.
(5) required to submit the design report, in accordance with the standard format deep experimental report, also need to code, the simulation results and the integrated circuit diagram.
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File list (Check if you may need any files):
加法器\CLA_Adder.png
......\CLA_Adder.txt
......\adder.txt
......\adder_cripple.png
......\adder_cripple.txt
......\zuoye.txt
加法器
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