Description: Achieve a synchronous fifo with verilog design, compression bag has the role of word describes the design of the signals
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File list (Check if you may need any files):
同步FIFO设计\fifo\fifo.cr.mti
............\....\fifo.mpf
............\....\fifo.v
............\....\fifo.v.bak
............\....\fifo_16_8.v
............\....\fifo_16_8.v.bak
............\....\fifo_64_8.v.bak
............\....\fifo_tb4.v
............\....\fifo_tb4.v.bak
............\....\half_full_logic.txt
............\....\next_pos.txt
............\....\vsim.wlf
............\....\wave.bmp
............\....\wave2_syn.bmp
............\....\.ork\fifo\verilog.prw
............\....\....\....\verilog.psm
............\....\....\....\_primary.dat
............\....\....\....\_primary.dbs
............\....\....\....\_primary.vhd
............\....\....\...._16_8\verilog.prw
............\....\....\.........\verilog.psm
............\....\....\.........\_primary.dat
............\....\....\.........\_primary.dbs
............\....\....\.........\_primary.vhd
............\....\....\testbench_fifo_final\verilog.prw
............\....\....\....................\verilog.psm
............\....\....\....................\_primary.dat
............\....\....\....................\_primary.dbs
............\....\....\....................\_primary.vhd
............\....\....\_info
............\....\....\.temp\vlogjj31sg
............\....\....\.....\vlogscega9
............\....\....\.....\vlogye6c3k
............\....\....\_vmake
............\fifo_1.v
............\fifo_tb.v
............\wave4.bmp
............\实验报告三.doc
............\fifo\work\fifo
............\....\....\fifo_16_8
............\....\....\testbench_fifo_final
............\....\....\_temp
............\....\work
............\fifo
同步FIFO设计
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