Description: Multirate digital signal processing system which includes
sampling rate conversion. This technique is necessary for
systems with different input and output sampling rates, as the
proposed multirate device is downsampler FPGA
implementation of the same is presented. The FPGA synthesis
results are verified and report is presented. In order to build
down sampler consisting of D F/F and clock generator, are
downloaded on cyclone-II FPGA
To Search:
File list (Check if you may need any files):
dwn_sampler\Divideby_N.v
...........\Downsampler.v
...........\Downsampler_tb.v
Download