RS(204-188)decoder_verilog Verilog achieved using

Title: RS(204-188)decoder_verilog

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
14kb
Update:
2016-06-13
Downloads:
0 Times
Uploaded by:
刘建涛

Description: Verilog achieved using the finite field GF (28) weak dual basis multiplier

Downloaders recently: [More information of uploader 刘建涛]

To Search:

File list (Check if you may need any files):

Filename Size Date
RS(204 188)译码器verilog设计\code\BM_KES.v
............................\....\CheinSearch.v
............................\....\ff_mul.v
............................\....\forney.v
............................\....\ROM_INV.mif
............................\....\rom_inv.v
............................\....\rom_power.mif
............................\....\rom_power.v
............................\....\RS(204 188)译码器说明.txt
............................\....\rs_decoder.v
............................\....\SyndromeCalc.v
............................\code
RS(204 188)译码器verilog设计

Main Category

SourceCode

Web Code

Develop Tools

Document

Other resource

Category

About site

CodeBus www.codebus.net

Filename	Size	Date
RS(204	188)译码器verilog设计\code\BM_KES.v
............................\....\CheinSearch.v
............................\....\ff_mul.v
............................\....\forney.v
............................\....\ROM_INV.mif
............................\....\rom_inv.v
............................\....\rom_power.mif
............................\....\rom_power.v
............................\....\RS(204	188)译码器说明.txt
............................\....\rs_decoder.v
............................\....\SyndromeCalc.v
............................\code
RS(204	188)译码器verilog设计