- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 12kb
- Update:
- 2016-01-22
- Downloads:
- 0 Times
- Uploaded by:
- 毕向伟
Description: UART VHDL sources with FIFO,baudrate,receiver,transmitter,register,testbench
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File list (Check if you may need any files):
uartlvds
........\baud_rate.vhd
........\fifo_lvds.vhd
........\lvdc_top.vhd
........\receiver_lvds.vhd
........\tb_lvds_top.vhd
........\transmitter_lvds.vhd
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