Title:
Signal-Generator-VHDL-design
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- Category:
- VHDL-FPGA-Verilog
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- File Size:
- 741kb
- Update:
- 2016-05-15
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Description: Optional waveform signal generator VHDL design: sinusoidal (sine), square wave (sqr), sawtooth (jc_de and jc_in two kinds), triangle wave (sanj) and staircase (stair) signal modules
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信号发生器VHDL设计.docx
