Description: VDHL written by a 25th order symmetric FIR filter in Seke Long 3FPGA under verify that no problem (AD sampling clock 50Mhz, this design is a bit of hardware requirements), which calls the multiplier official API, can be used to save resources CSD encoding conversion multiplier can be reduced by more than half of the resources
To Search:
File list (Check if you may need any files):
fir25.vhd
Download