Description: Based on vivado Verilog pseudo random number generator, using LFSR algorithm, and upgrade it, using the idea of feedback cascade, from the maximum cycle of 2^n to 3-5 times the original
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pseudo_random\pseudo_random.cache\wt\java_command_handlers.wdf
pseudo_random\pseudo_random.cache\wt\synthesis.wdf
pseudo_random\pseudo_random.cache\wt\synthesis_details.wdf
pseudo_random\pseudo_random.cache\wt\webtalk_pa.xml
pseudo_random\pseudo_random.cache\wt\xsim.wdf
pseudo_random\pseudo_random.runs\.jobs\vrs_config_1.xml
pseudo_random\pseudo_random.runs\.jobs\vrs_config_2.xml
pseudo_random\pseudo_random.runs\.jobs\vrs_config_3.xml
pseudo_random\pseudo_random.runs\.jobs\vrs_config_4.xml
pseudo_random\pseudo_random.runs\.jobs\vrs_config_5.xml
pseudo_random\pseudo_random.runs\.jobs\vrs_config_6.xml
pseudo_random\pseudo_random.runs\.jobs\vrs_config_7.xml
pseudo_random\pseudo_random.runs\.jobs\vrs_config_8.xml
pseudo_random\pseudo_random.runs\synth_1\.vivado.begin.rst
pseudo_random\pseudo_random.runs\synth_1\.vivado.end.rst
pseudo_random\pseudo_random.runs\synth_1\.Vivado_Synthesis.queue.rst
pseudo_random\pseudo_random.runs\synth_1\gen_run.xml
pseudo_random\pseudo_random.runs\synth_1\htr.txt
pseudo_random\pseudo_random.runs\synth_1\ISEWrap.js
pseudo_random\pseudo_random.runs\synth_1\ISEWrap.sh
pseudo_random\pseudo_random.runs\synth_1\project.wdf
pseudo_random\pseudo_random.runs\synth_1\rundef.js
pseudo_random\pseudo_random.runs\synth_1\runme.bat
pseudo_random\pseudo_random.runs\synth_1\runme.log
pseudo_random\pseudo_random.runs\synth_1\runme.sh
pseudo_random\pseudo_random.runs\synth_1\top.dcp
pseudo_random\pseudo_random.runs\synth_1\top.tcl
pseudo_random\pseudo_random.runs\synth_1\top.vds
pseudo_random\pseudo_random.runs\synth_1\top_utilization_synth.pb
pseudo_random\pseudo_random.runs\synth_1\top_utilization_synth.rpt
pseudo_random\pseudo_random.runs\synth_1\vivado.jou
pseudo_random\pseudo_random.runs\synth_1\vivado.pb
pseudo_random\pseudo_random.sim\sim_1\behav\compile.bat
pseudo_random\pseudo_random.sim\sim_1\behav\compile.log
pseudo_random\pseudo_random.sim\sim_1\behav\elaborate.bat
pseudo_random\pseudo_random.sim\sim_1\behav\elaborate.log
pseudo_random\pseudo_random.sim\sim_1\behav\glbl.v
pseudo_random\pseudo_random.sim\sim_1\behav\simulate.log
pseudo_random\pseudo_random.sim\sim_1\behav\tb_behav.wdb
pseudo_random\pseudo_random.sim\sim_1\behav\tb_lfsr_behav.wdb
pseudo_random\pseudo_random.sim\sim_1\behav\tb_vlog.prj
pseudo_random\pseudo_random.sim\sim_1\behav\xelab.pb
pseudo_random\pseudo_random.sim\sim_1\behav\xsim.dir\tb_behav\tb_behav_17684_1506887636.btree
pseudo_random\pseudo_random.sim\sim_1\behav\xsim.dir\tb_behav\webtalk\.xsim_webtallk.info
pseudo_random\pseudo_random.sim\sim_1\behav\xsim.dir\tb_behav\xsim.mem
pseudo_random\pseudo_random.sim\sim_1\behav\xsim.dir\tb_behav\xsim.reloc
pseudo_random\pseudo_random.sim\sim_1\behav\xsim.dir\tb_behav\xsim.type
pseudo_random\pseudo_random.sim\sim_1\behav\xsim.dir\tb_behav\xsim.xdbg
pseudo_random\pseudo_random.sim\sim_1\behav\xsim.dir\tb_behav\xsimcrash.log
pseudo_random\pseudo_random.sim\sim_1\behav\xsim.dir\tb_behav\xsimk.exe
pseudo_random\pseudo_random.sim\sim_1\behav\xsim.dir\tb_behav\xsimkernel.log
pseudo_random\pseudo_random.sim\sim_1\behav\xsim.dir\tb_lfsr_behav\tb_lfsr_behav_17684_1506875797.btree
pseudo_random\pseudo_random.sim\sim_1\behav\xsim.dir\tb_lfsr_behav\xsim.xdbg
pseudo_random\pseudo_random.sim\sim_1\behav\xsim.dir\xil_defaultlib\glbl.sdb
pseudo_random\pseudo_random.sim\sim_1\behav\xsim.dir\xil_defaultlib\random.sdb
pseudo_random\pseudo_random.sim\sim_1\behav\xsim.dir\xil_defaultlib\tb.sdb
pseudo_random\pseudo_random.sim\sim_1\behav\xsim.dir\xil_defaultlib\top.sdb
pseudo_random\pseudo_random.sim\sim_1\behav\xsim.dir\xsim.svtype
pseudo_random\pseudo_random.sim\sim_1\behav\xvlog.pb
pseudo_random\pseudo_random.srcs\sim_1\imports\new\tb.v
pseudo_random\pseudo_random.srcs\sources_1\new\random.v
pseudo_random\pseudo_random.srcs\sources_1\new\random2.v
pseudo_random\pseudo_random.srcs\sources_1\new\top.v
pseudo_random\pseudo_random.xpr
pseudo_random\pseudo_random2\project_1\project_1.cache\wt\java_command_handlers.wdf
pseudo_random\pseudo_random2\project_1\project_1.cache\wt\synthesis.wdf
pseudo_random\pseudo_random2\project_1\project_1.cache\wt\synthesis_details.wdf
pseudo_random\pseudo_random2\project_1\project_1.cache\wt\webtalk_pa.xml
pseudo_random\pseudo_random2\project_1\project_1.cache\wt\xsim.wdf
pseudo_random\pseudo_random2\project_1\project_1.hw\hw_1\hw.xml
pseudo_random\pseudo_random2\project_1\project_1.runs\.jobs\vrs_config_1.xml
pseudo_random\pseudo_random2\project_1\project_1.runs\.jobs\vrs_config_10.xml
pseudo_random\pseudo_random2\project_1\project_1.runs\.jobs\vrs_config_11.xml
pseudo_random\pseudo_random2\project_1\project_1.runs\.jobs\vrs_config_2.xml
pseudo_random\pseudo_random2\project_1\project_1.runs\.jobs\vrs_config_3.xml
pseudo_random\pseudo_random2\project_1\project_1.runs\.jobs\vrs_config_4.xml
pseudo_random\pseudo_random2\project_1\project_1.runs\.jobs\vrs_config_5.xml
pseudo_random\pseudo_random2\project_1\project_1.runs\.jobs\vrs_config_6.xml
pseudo_random\pseudo_random2\project_1\project_1.runs\.jobs\vrs_config_7.xml
pseudo_random\pseudo_random2\project_1\project_1.runs\.jobs\vrs_config_8.xml
pseudo_random\pseudo_random2\project_1\project_1.runs\.jobs\vrs_config_9.xml
pseudo_random\pseudo_random2\project_1\project_1.runs\impl_1\.init_design.begin.rst
pseudo_random\pseudo_random2\project_1\project_1.runs\impl_1\.init_design.end.rst
pseudo_random\pseudo_random2\project_1\project_1.runs\impl_1\.opt_design.begin.rst
pseudo_random\pseudo_random2\project_1\project_1.runs\impl_1\.opt_design.end.rst
pseudo_random\pseudo_random2\project_1\project_1.runs\impl_1\.place_design.begin.rst
pseudo_random\pseudo_random2\project_1\project_1.runs\impl_1\.place_design.end.rst
pseudo_random\pseudo_random2\project_1\project_1.runs\impl_1\.route_design.begin.rst
pseudo_random\pseudo_random2\project_1\project_1.runs\impl_1\.route_design.end.rst
pseudo_random\pseudo_random2\project_1\project_1.runs\impl_1\.vivado.begin.rst
pseudo_random\pseudo_random2\project_1\project_1.runs\impl_1\.vivado.end.rst
pseudo_random\pseudo_random2\project_1\project_1.runs\impl_1\.Vivado_Implementation.queue.rst
pseudo_random\pseudo_random2\project_1\project_1.runs\impl_1\.write_bitstream.begin.rst
pseudo_random\pseudo_random2\project_1\project_1.runs\impl_1\.write_bitstream.end.rst
pseudo_random\pseudo_random2\project_1\project_1.runs\impl_1\gen_run.xml
pseudo_random\pseudo_random2\project_1\project_1.runs\impl_1\htr.txt
pseudo_random\pseudo_random2\project_1\project_1.runs\impl_1\init_design.pb
pseudo_random\pseudo_random2\project_1\project_1.runs\impl_1\ISEWrap.js
pseudo_random\pseudo_random2\project_1\project_1.runs\impl_1\ISEWrap.sh
pseudo_random\pseudo_random2\project_1\project_1.runs\impl_1\opt_design.pb
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