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Title: VHDL_SPISLAVE Download
 Description: VHDL implementation of spi-slave communication
 Downloaders recently: [More information of uploader 姚粤]
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FilenameSizeDate
VHDL_SPISLAVE
VHDL_SPISLAVE\db
VHDL_SPISLAVE\db\logic_util_heursitic.dat 6952 2016-12-05
VHDL_SPISLAVE\db\prev_cmp_TEST.qmsg 102492 2016-12-05
VHDL_SPISLAVE\db\TEST.db_info 137 2016-12-07
VHDL_SPISLAVE\incremental_db
VHDL_SPISLAVE\incremental_db\compiled_partitions
VHDL_SPISLAVE\incremental_db\compiled_partitions\TEST.db_info 138 2016-12-05
VHDL_SPISLAVE\incremental_db\compiled_partitions\TEST.root_partition.cmp.cdb 7139 2016-12-05
VHDL_SPISLAVE\incremental_db\compiled_partitions\TEST.root_partition.cmp.dfp 33 2016-12-05
VHDL_SPISLAVE\incremental_db\compiled_partitions\TEST.root_partition.cmp.hdb 11886 2016-12-05
VHDL_SPISLAVE\incremental_db\compiled_partitions\TEST.root_partition.cmp.kpt 199 2016-12-05
VHDL_SPISLAVE\incremental_db\compiled_partitions\TEST.root_partition.cmp.logdb 4 2016-12-05
VHDL_SPISLAVE\incremental_db\compiled_partitions\TEST.root_partition.cmp.rcfdb 7756 2016-12-05
VHDL_SPISLAVE\incremental_db\compiled_partitions\TEST.root_partition.map.cdb 4408 2016-12-05
VHDL_SPISLAVE\incremental_db\compiled_partitions\TEST.root_partition.map.dpi 862 2016-12-05
VHDL_SPISLAVE\incremental_db\compiled_partitions\TEST.root_partition.map.hbdb.cdb 604 2016-12-05
VHDL_SPISLAVE\incremental_db\compiled_partitions\TEST.root_partition.map.hbdb.hb_info 46 2016-12-05
VHDL_SPISLAVE\incremental_db\compiled_partitions\TEST.root_partition.map.hbdb.hdb 11132 2016-12-05
VHDL_SPISLAVE\incremental_db\compiled_partitions\TEST.root_partition.map.hbdb.sig 31 2016-12-05
VHDL_SPISLAVE\incremental_db\compiled_partitions\TEST.root_partition.map.hdb 11151 2016-12-05
VHDL_SPISLAVE\incremental_db\compiled_partitions\TEST.root_partition.map.kpt 933 2016-12-05
VHDL_SPISLAVE\incremental_db\README 653 2016-12-05
VHDL_SPISLAVE\simulation
VHDL_SPISLAVE\simulation\modelsim
VHDL_SPISLAVE\simulation\modelsim\modelsim.ini 75926 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\msim_transcript 41181 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt0d546k 164 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt0ta8c8 2044 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt18t2bh 8521 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt1mz6h5 1064 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt1vky4x 8620 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt23f1ge 37080 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt2a8c85 3609 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt2gk5n2 1536 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt2n9x9t 23625 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt3b94vz 12112 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt3fciwq 5887 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt3hyveq 13161 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt3y30mb 39464 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt4cjtjk 1890 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt4kgrga 3087 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt4srys8 22320 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt51j15t 13525 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt578srh 3714 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt5kdxy5 15016 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt62xqxe 5088 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt6f2w33 22336 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt7aqt80 14248 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt7gciwq 482 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt7xhn2c 48 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt85csdx 28120 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt8b1h1m 20171 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt8d1h1m 1505 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt8r6m79 168 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt901rit 598440 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt96nf6i 680 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt9jvjc6 3455 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopt9wky4x 306 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopta1bebf 4233 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptab8c85 4701 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptaegih3 1669 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptb95hn0 1791 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptbnamwk 2819 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptbwzcgc 2712 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptc4tfvx 2871 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptcqkbm9 164 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptd546ki 120 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptdi9at6 1204 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptdzee0v 1335 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopte0s4sf 696 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptedy8z3 2984 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptet3d5r 3536 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptf8j741 48 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptfmrbam 29315 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptfvd3yc 1922 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptg3869y 1388 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptgn223a 1155 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopthhq087 1377 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopthyw4ev 798 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\vopticczc4 3648 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptish3jr 603 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptj71yh1 48 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptj7xad2 14879 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptjk62rm 1104 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptk2nwny 148 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptkfv0xi 452 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptkmgrga 6592 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptkngrga 16120 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptm546ki 1965 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptmagz1g 1227 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptmg5qm7 1892 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptmxavvv 5332 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptn55y6d 1921 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptnbtmt4 962 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptnrzs0s 4200 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptq6fkz1 4543 2016-12-06
VHDL_SPISLAVE\simulation\modelsim\rtl_work\@_opt\voptqjkr5n 3076 2016-12-06

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