Description: Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.
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File list (Check if you may need any files):
sobel\design\fifo_ctrl.v
sobel\design\greybox_tmp\cbx_args.txt
sobel\design\ram_ctrl.v
sobel\design\sobel_top.v
sobel\design\uart_rx.v
sobel\design\uart_tx.v
sobel\design\vga_disp.v
sobel\design\vga_drive.v
sobel\doc\fifo输出数据时各信号截图.png
sobel\doc\Sobel模块框图.vsdx
sobel\doc\VS038A.tmp
sobel\doc\VS054C4.tmp
sobel\doc\VS05CB7.tmp
sobel\doc\VS05FD0.tmp
sobel\doc\VS0683B.tmp
sobel\doc\VS086D2.tmp
sobel\doc\VS0891E.tmp
sobel\doc\VS092DD.tmp
sobel\doc\VS0A40F.tmp
sobel\doc\VS0C94D.tmp
sobel\doc\VS0E351.tmp
sobel\doc\波形图.vsdx
sobel\ipcore_dir\fifo.qip
sobel\ipcore_dir\fifo.v
sobel\ipcore_dir\fifo_inst.v
sobel\ipcore_dir\pll_25M.qip
sobel\ipcore_dir\pll_25M.v
sobel\ipcore_dir\pll_25M_inst.v
sobel\ipcore_dir\ram_8x39204.qip
sobel\ipcore_dir\ram_8x39204.v
sobel\ipcore_dir\ram_8x39204_inst.v
sobel\matlab\cablecar.jpg
sobel\matlab\cablecar.txt
sobel\matlab\castle1.jpg
sobel\matlab\castle1.txt
sobel\matlab\castle2.jpg
sobel\matlab\castle2.txt
sobel\matlab\create.m
sobel\matlab\flowers.jpg
sobel\matlab\flowers.txt
sobel\matlab\miku.jpg
sobel\matlab\miku.txt
sobel\matlab\txxh.jpg
sobel\matlab\txxh.txt
sobel\matlab\标测图像\aerial.jpg
sobel\matlab\标测图像\airfield.jpg
sobel\matlab\标测图像\airfield2.jpg
sobel\matlab\标测图像\airplaneU2.jpg
sobel\matlab\标测图像\baboon.jpg
sobel\matlab\标测图像\barbara.jpg
sobel\matlab\标测图像\boats.jpg
sobel\matlab\标测图像\BoatsColor.jpg
sobel\matlab\标测图像\bridge.jpg
sobel\matlab\标测图像\cablecar.jpg
sobel\matlab\标测图像\castle1.jpg
sobel\matlab\标测图像\castle2.jpg
sobel\matlab\标测图像\castle3.jpg
sobel\matlab\标测图像\castle4.jpg
sobel\matlab\标测图像\flowers.jpg
sobel\matlab\标测图像\fruits.jpg
sobel\matlab\标测图像\goldhill.jpg
sobel\matlab\标测图像\lena.jpg
sobel\matlab\标测图像\monarch.jpg
sobel\matlab\标测图像\pepper.jpg
sobel\matlab\标测图像\yacht.jpg
sobel\outdata.mif
sobel\pin.txt
sobel\quartus_prj\db\.cmp.kpt
sobel\quartus_prj\db\altsyncram_4rf1.tdf
sobel\quartus_prj\db\altsyncram_arf1.tdf
sobel\quartus_prj\db\altsyncram_jls1.tdf
sobel\quartus_prj\db\altsyncram_obq1.tdf
sobel\quartus_prj\db\altsyncram_ups1.tdf
sobel\quartus_prj\db\a_dpfifo_0s71.tdf
sobel\quartus_prj\db\a_dpfifo_tr71.tdf
sobel\quartus_prj\db\cmpr_ks8.tdf
sobel\quartus_prj\db\cmpr_ls8.tdf
sobel\quartus_prj\db\cntr_0ab.tdf
sobel\quartus_prj\db\cntr_1ab.tdf
sobel\quartus_prj\db\cntr_ca7.tdf
sobel\quartus_prj\db\cntr_da7.tdf
sobel\quartus_prj\db\cntr_v9b.tdf
sobel\quartus_prj\db\decode_h8a.tdf
sobel\quartus_prj\db\decode_osa.tdf
sobel\quartus_prj\db\logic_util_heursitic.dat
sobel\quartus_prj\db\mux_8nb.tdf
sobel\quartus_prj\db\pll_25M_altpll.v
sobel\quartus_prj\db\prev_cmp_sobel_top.qmsg
sobel\quartus_prj\db\quartus_fit.exe.0.tmp
sobel\quartus_prj\db\scfifo_a481.tdf
sobel\quartus_prj\db\scfifo_d481.tdf
sobel\quartus_prj\db\sobel_top.db_info
sobel\quartus_prj\db\sobel_top.ipinfo
sobel\quartus_prj\db\sobel_top.sld_design_entry.sci
sobel\quartus_prj\incremental_db\compiled_partitions\sobel_top.db_info
sobel\quartus_prj\incremental_db\README
sobel\quartus_prj\output_files\greybox_tmp\cbx_args.txt
sobel\quartus_prj\output_files\sobel.jic
sobel\quartus_prj\output_files\sobel.map
sobel\quartus_prj\output_files\sobel_top.asm.rpt
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