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VHDL-FPGA-Verilog
Title:
syn_fifo
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Category:
VHDL-FPGA-Verilog
Tags:
[VHDL]
[源码]
File Size:
1kb
Update:
2017-07-07
Downloads:
0 Times
Uploaded by:
杨启航
Description:
The source package is a synchronous FIFO Verilog language model, including 2 main parts: synchronous FIFO control module, test files.
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More information of uploader 杨启航
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tb_fifo.v syn_fifo.v
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