Description: Using Verilog to realize digital stopwatch (basic logic design frequency divider practice)
Set the reset switch. When the reset switch is pressed, the stopwatch is zero and the timing is ready. In any case, as long as we press the reset switch, the stopwatch is unconditionally reset operation, even in the process of timing, we must do zero clearing operation without any conditions.
Set up / stop switch. When the start / stop switch is pressed, the stopwatch output will be started. When the start / stop switch is pressed, the stopwatch output will be terminated.
The structure design style is described, that is, first design a 10 frequency division circuit, then use this circuit to build a stopwatch circuit.
To Search:
File list (Check if you may need any files):
| Filename | Size | Date |
|---|
| FrequencyDivision10.v | 243 | 2018-01-30
|
| SecondClk.v | 355 | 2018-01-30
|
| StopWatch.v | 343 | 2018-01-30
|
| StopWatchTest.v | 380 | 2018-01-30
|
| Counter.v | 844 | 2018-01-29 |
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