- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 34kb
- Update:
- 2018-01-31
- Downloads:
- 0 Times
- Uploaded by:
- 未曾走远
Description: Its use of the module's code style to write, to 8 dct conversion
To Search:
File list (Check if you may need any files):
Filename | Size | Date |
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verilog dct | 0 | 2018-01-29
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verilog dct\dct | 0 | 2018-01-29
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verilog dct\dct\dct.v | 9323 | 2005-11-30
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verilog dct\dct\dct_mac.v | 4454 | 2005-11-30
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verilog dct\dct\dct_syn.v | 3904 | 2005-11-30
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verilog dct\dct\dctu.v | 251256 | 2005-11-30
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verilog dct\dct\dctub.v | 4690 | 2005-11-30
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verilog dct\dct\fdct.v | 9750 | 2005-11-30
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verilog dct\dct\ro_cnt.v | 3927 | 2005-11-30
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verilog dct\dct\ud_cnt.v | 3942 | 2005-11-30
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verilog dct\dct\zigzag.v | 7807 | 2005-11-30
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verilog dct\top1.rar | 1316 | 2010-02-27
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verilog dct\top1.v | 4733 | 2010-02-27 |