Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: oo Download
  • Category:
  • VHDL-FPGA-Verilog
  • Tags:
  • File Size:
  • 41.16mb
  • Update:
  • 2018-04-02
  • Downloads:
  • 0 Times
  • Uploaded by:
  • 薇
 Description: We use the vivado platform developed by Xilinx to realize the down conversion function.
 Downloaders recently: [More information of uploader 薇]
 To Search:
File list (Check if you may need any files): 
FilenameSizeDate
oo\oo.cache\ip\2017.4\04d77bae0011540a\04d77bae0011540a.xci 12783  2018-03-26

oo\oo.cache\ip\2017.4\04d77bae0011540a\rom16.dcp 132681  2018-03-26

oo\oo.cache\ip\2017.4\04d77bae0011540a\rom16_sim_netlist.v 202695  2018-03-26

oo\oo.cache\ip\2017.4\04d77bae0011540a\rom16_sim_netlist.vhdl 238198  2018-03-26

oo\oo.cache\ip\2017.4\04d77bae0011540a\rom16_stub.v 1329  2018-03-26

oo\oo.cache\ip\2017.4\04d77bae0011540a\rom16_stub.vhdl 1464  2018-03-26

oo\oo.cache\ip\2017.4\04d77bae0011540a.logs\runme.log 37136  2018-03-26

oo\oo.cache\ip\2017.4\240847cbae43d9a9\240847cbae43d9a9.xci 12774  2018-03-21

oo\oo.cache\ip\2017.4\240847cbae43d9a9\rom16.dcp 101315  2018-03-21

oo\oo.cache\ip\2017.4\240847cbae43d9a9\rom16_sim_netlist.v 172599  2018-03-21

oo\oo.cache\ip\2017.4\240847cbae43d9a9\rom16_sim_netlist.vhdl 195438  2018-03-21

oo\oo.cache\ip\2017.4\240847cbae43d9a9\rom16_stub.v 1327  2018-03-21

oo\oo.cache\ip\2017.4\240847cbae43d9a9\rom16_stub.vhdl 1458  2018-03-21

oo\oo.cache\ip\2017.4\240847cbae43d9a9\stats.txt 55  2018-03-28

oo\oo.cache\ip\2017.4\240847cbae43d9a9.logs\runme.log 36671  2018-03-21

oo\oo.cache\ip\2017.4\5eab1d382ddd3e84\5eab1d382ddd3e84.xci 6158  2018-03-22

oo\oo.cache\ip\2017.4\5eab1d382ddd3e84\mult.dcp 18598  2018-03-22

oo\oo.cache\ip\2017.4\5eab1d382ddd3e84\mult_sim_netlist.v 22774  2018-03-22

oo\oo.cache\ip\2017.4\5eab1d382ddd3e84\mult_sim_netlist.vhdl 32994  2018-03-22

oo\oo.cache\ip\2017.4\5eab1d382ddd3e84\mult_stub.v 1322  2018-03-22

oo\oo.cache\ip\2017.4\5eab1d382ddd3e84\mult_stub.vhdl 1491  2018-03-22

oo\oo.cache\ip\2017.4\5eab1d382ddd3e84.logs\runme.log 17668  2018-03-22

oo\oo.cache\ip\2017.4\7d303fe8fd36e824\7d303fe8fd36e824.xci 12799  2018-03-28

oo\oo.cache\ip\2017.4\7d303fe8fd36e824\blk_mem_gen_0.dcp 133343  2018-03-28

oo\oo.cache\ip\2017.4\7d303fe8fd36e824\blk_mem_gen_0_sim_netlist.v 202731  2018-03-28

oo\oo.cache\ip\2017.4\7d303fe8fd36e824\blk_mem_gen_0_sim_netlist.vhdl 238234  2018-03-28

oo\oo.cache\ip\2017.4\7d303fe8fd36e824\blk_mem_gen_0_stub.v 1345  2018-03-28

oo\oo.cache\ip\2017.4\7d303fe8fd36e824\blk_mem_gen_0_stub.vhdl 1480  2018-03-28

oo\oo.cache\ip\2017.4\7d303fe8fd36e824.logs\runme.log 37209  2018-03-28

oo\oo.cache\ip\2017.4\afe3be7560113b98\afe3be7560113b98.xci 14251  2018-03-22

oo\oo.cache\ip\2017.4\afe3be7560113b98\duc_ddc_compiler_0.dcp 1433550  2018-03-22

oo\oo.cache\ip\2017.4\afe3be7560113b98\duc_ddc_compiler_0_sim_netlist.v 13981784  2018-03-22

oo\oo.cache\ip\2017.4\afe3be7560113b98\duc_ddc_compiler_0_sim_netlist.vhdl 14283665  2018-03-22

oo\oo.cache\ip\2017.4\afe3be7560113b98\duc_ddc_compiler_0_stub.v 2402  2018-03-22

oo\oo.cache\ip\2017.4\afe3be7560113b98\duc_ddc_compiler_0_stub.vhdl 2478  2018-03-22

oo\oo.cache\ip\2017.4\afe3be7560113b98.logs\runme.log 206934  2018-03-22

oo\oo.cache\ip\2017.4\c1b5d4ebb0178c5d\c1b5d4ebb0178c5d.xci 12772  2018-03-21

oo\oo.cache\ip\2017.4\c1b5d4ebb0178c5d\rom16.dcp 105999  2018-03-21

oo\oo.cache\ip\2017.4\c1b5d4ebb0178c5d\rom16_sim_netlist.v 181553  2018-03-21

oo\oo.cache\ip\2017.4\c1b5d4ebb0178c5d\rom16_sim_netlist.vhdl 203510  2018-03-21

oo\oo.cache\ip\2017.4\c1b5d4ebb0178c5d\rom16_stub.v 1395  2018-03-21

oo\oo.cache\ip\2017.4\c1b5d4ebb0178c5d\rom16_stub.vhdl 1531  2018-03-21

oo\oo.cache\ip\2017.4\c1b5d4ebb0178c5d.logs\runme.log 50916  2018-03-21

oo\oo.cache\wt\gui_handlers.wdf 9757  2018-04-02

oo\oo.cache\wt\java_command_handlers.wdf 2502  2018-04-02

oo\oo.cache\wt\project.wpc 62  2018-04-02

oo\oo.cache\wt\synthesis.wdf 5402  2018-03-28

oo\oo.cache\wt\webtalk_pa.xml 8620  2018-04-02

oo\oo.cache\wt\xsim.wdf 256  2018-03-26

oo\oo.hw\oo.lpr 290  2018-03-21

oo\oo.ip_user_files\ip\blk_mem_gen_0\blk_mem_gen_0.veo 2985  2018-03-28

oo\oo.ip_user_files\ip\blk_mem_gen_0\blk_mem_gen_0.vho 3228  2018-03-28

oo\oo.ip_user_files\ip\blk_mem_gen_0\blk_mem_gen_0_stub.v 1273  2018-03-28

oo\oo.ip_user_files\ip\blk_mem_gen_0\blk_mem_gen_0_stub.vhdl 1352  2018-03-28

oo\oo.ip_user_files\ip\duc_ddc_compiler_0\duc_ddc_compiler_0.veo 4371  2018-03-26

oo\oo.ip_user_files\ip\duc_ddc_compiler_0\duc_ddc_compiler_0.vho 4592  2018-03-26

oo\oo.ip_user_files\ip\duc_ddc_compiler_0\duc_ddc_compiler_0_stub.v 2340  2018-03-22

oo\oo.ip_user_files\ip\duc_ddc_compiler_0\duc_ddc_compiler_0_stub.vhdl 2370  2018-03-22

oo\oo.ip_user_files\ip\mult\mult.veo 2972  2018-03-26

oo\oo.ip_user_files\ip\mult\mult.vho 3215  2018-03-26

oo\oo.ip_user_files\ip\mult\mult_stub.v 1214  2018-03-22

oo\oo.ip_user_files\ip\mult\mult_stub.vhdl 1309  2018-03-22

oo\oo.ip_user_files\ip\rom16\rom16.veo 2960  2018-03-28

oo\oo.ip_user_files\ip\rom16\rom16.vho 3195  2018-03-28

oo\oo.ip_user_files\ipstatic\hdl\duc_ddc_compiler_v3_0_vh_rfs.vhd 1499235  2018-03-22

oo\oo.ip_user_files\ipstatic\hdl\fir_compiler_v5_2_vh_rfs.vhd 3685342  2018-03-22

oo\oo.ip_user_files\ipstatic\hdl\mult_gen_v12_0_vh_rfs.vhd 1310888  2018-03-22

oo\oo.ip_user_files\ipstatic\hdl\xbip_bram18k_v3_0_vh_rfs.vhd 103702  2018-03-22

oo\oo.ip_user_files\ipstatic\hdl\xbip_pipe_v3_0_vh_rfs.vhd 30625  2018-03-22

oo\oo.ip_user_files\ipstatic\hdl\xbip_utils_v3_0_vh_rfs.vhd 171224  2018-03-22

oo\oo.ip_user_files\ipstatic\simulation\blk_mem_gen_v8_4.v 171256  2018-03-21

oo\oo.ip_user_files\mem_init_files\blk_mem_gen_0.mif 304095  2018-03-28

oo\oo.ip_user_files\mem_init_files\ddc_chbw5_C1_pb5_if0_frf153_os2.cfg 235  2018-03-26

oo\oo.ip_user_files\mem_init_files\ddc_chbw5_C1_pb5_if0_frf153_os2_s1.mif 133  2018-03-26

oo\oo.ip_user_files\mem_init_files\ddc_chbw5_C1_pb5_if0_frf153_os2_s2.mif 133  2018-03-26

oo\oo.ip_user_files\mem_init_files\ddc_chbw5_C1_pb5_if0_frf153_os2_s3.mif 1121  2018-03-26

oo\oo.ip_user_files\mem_init_files\ddc_chbw5_C1_pb5_if0_frf153_os2_s4.mif 2147  2018-03-26

oo\oo.ip_user_files\mem_init_files\PWM.coe 1474536  2018-03-28

oo\oo.ip_user_files\mem_init_files\PWM_phase0.coe 331805  2018-03-28

oo\oo.ip_user_files\mem_init_files\rom16.mif 589788  2018-03-28

oo\oo.ip_user_files\mem_init_files\summary.log 904  2018-03-28

oo\oo.ip_user_files\README.txt 130  2018-03-21

oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\blk_mem_gen_0.mif 304095  2018-03-28

oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\blk_mem_gen_0.sh 4899  2018-03-28

oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\blk_mem_gen_0.udo 0  2018-03-28

oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\compile.do 680  2018-03-28

oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\file_info.txt 427  2018-03-28

oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\glbl.v 1474  2017-12-14

oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\PWM_phase0.coe 331805  2018-03-28

oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\README.txt 2201  2018-03-28

oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\simulate.do 340  2018-03-28

oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\summary.log 904  2018-03-28

oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\activehdl\wave.do 32  2018-03-28

oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\ies\blk_mem_gen_0.mif 304095  2018-03-28

oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\ies\blk_mem_gen_0.sh 5713  2018-03-28

oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\ies\file_info.txt 427  2018-03-28

oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\ies\glbl.v 1474  2017-12-14

oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\ies\PWM_phase0.coe 331805  2018-03-28

oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\ies\README.txt 2142  2018-03-28

oo\oo.ip_user_files\sim_scripts\blk_mem_gen_0\ies\run.f 487  2018-03-28

CodeBus www.codebus.net