- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 1kb
- Update:
- 2018-04-18
- Downloads:
- 0 Times
- Uploaded by:
- 明日子
Description: The code implements the 255 bit decoder on the Basys2 board with Verilog language, encoding from SW0~SW7 input and LED lamp time to display decoding content.
To Search:
File list (Check if you may need any files):
| Filename | Size | Date |
|---|
| Count_255_Implementation.txt | 546 | 2018-04-18
|
| Count_255.txt | 1194 | 2018-04-18 |
Download